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FLEX10KA Datasheet(PDF) 63 Page - Altera Corporation |
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FLEX10KA Datasheet(HTML) 63 Page - Altera Corporation |
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63 / 128 page ![]() Altera Corporation 63 FLEX 10K Embedded Programmable Logic Device Family Data Sheet Table 36. Interconnect Timing Microparameters Note (1) Symbol Parameter Conditions tDIN2IOE Delay from dedicated input pin to IOE control input (7) tDCLK2LE Delay from dedicated clock pin to LE or EAB clock (7) tDIN2DATA Delay from dedicated input or clock to LE or EAB data (7) tDCLK2IOE Delay from dedicated clock pin to IOE clock (7) tDIN2LE Delay from dedicated input pin to LE or EAB control input (7) tSAMELAB Routing delay for an LE driving another LE in the same LAB tSAMEROW Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the same row (7) tSAMECOLUMN Routing delay for an LE driving an IOE in the same column (7) tDIFFROW Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different row (7) tTWOROWS Routing delay for a row IOE or EAB driving an LE or EAB in a different row (7) tLEPERIPH Routing delay for an LE driving a control signal of an IOE via the peripheral control bus (7) tLABCARRY Routing delay for the carry-out signal of an LE driving the carry-in signal of a different LE in a different LAB tLABCASC Routing delay for the cascade-out signal of an LE driving the cascade-in signal of a different LE in a different LAB Table 37. External Timing Parameters Notes (8), (10) Symbol Parameter Conditions tDRR Register-to-register delay via four LEs, three row interconnects, and four local interconnects (9) tINSU Setup time with global clock at IOE register tINH Hold time with global clock at IOE register tOUTCO Clock-to-output delay with global clock at IOE register Table 38. External Bidirectional Timing Parameters Note (10) Symbol Parameter Condition tINSUBIDIR Setup time for bidirectional pins with global clock at adjacent LE register tINHBIDIR Hold time for bidirectional pins with global clock at adjacent LE register tOUTCOBIDIR Clock-to-output delay for bidirectional pins with global clock at IOE register tXZBIDIR Synchronous IOE output buffer disable delay tZXBIDIR Synchronous IOE output buffer enable delay, slow slew rate = off |
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