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FLEX10KA Datasheet(PDF) 23 Page - Altera Corporation |
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FLEX10KA Datasheet(HTML) 23 Page - Altera Corporation |
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23 / 128 page  Altera Corporation 23 FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figure 10. LE Clear & Preset Modes Asynchronous Clear The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this mode, the preset signal is tied to VCC to deactivate it. Asynchronous Clear Asynchronous Preset Asynchronous Clear & Preset Asynchronous Load without Clear or Preset PRN CLRN DQ NOT NOT Asynchronous Load with Clear PRN CLRN DQ NOT NOT Asynchronous Load with Preset NOT NOT PRN CLRN DQ PRN CLRN DQ VCC Chip-Wide Reset Chip-Wide Reset Chip-Wide Reset Chip-Wide Reset PRN CLRN DQ PRN CLRN DQ VCC Chip-WideReset Chip-Wide Reset labctrl1 or labctrl2 labctrl1 or labctrl2 labctrl1 (Asynchronous Load) labctrl1 (Asynchronous Load) labctrl1 (Asynchronous Load) data3 (Data) labctrl2 (Clear) labctrl2 (Preset) data3 (Data) data3 (Data) labctrl2 labctrl1 |
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