FLEX10KA datasheet(60/128 Pages) ALTERA

60 / 128 page

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

tSU

LE register setup time for data and enable signals before clock; LE register

recovery time after asynchronous clear, preset, or load

LE register hold time for data and enable signals after clock

tPRE

LE register preset delay

tCLR

LE register clear delay

tCH

Minimum clock high time from clock pin

tCL

Minimum clock low time from clock pin

Table 33. IOE Timing Microparameters

Note (1)

Symbol

Parameter

Conditions

tIOD

IOE data delay

tIOC

IOE register control signal delay

tIOCO

IOE register clock-to-output delay

tIOCOMB

IOE combinatorial delay

tIOSU

IOE register setup time for data and enable signals before clock; IOE register

recovery time after asynchronous clear

tIOH

IOE register hold time for data and enable signals after clock

tIOCLR

IOE register clear time

tOD1

Output buffer and pad delay, slow slew rate = off, VCCIO = VCCINT

C1 = 35 pF (2)

tOD2

Output buffer and pad delay, slow slew rate = off, VCCIO = low voltage

C1 = 35 pF (3)

tOD3

Output buffer and pad delay, slow slew rate = on

C1 = 35 pF (4)

tXZ

IOE output buffer disable delay

tZX1

IOE output buffer enable delay, slow slew rate = off, VCCIO = VCCINT

C1 = 35 pF (2)

tZX2

IOE output buffer enable delay, slow slew rate = off, VCCIO = low voltage

C1 = 35 pF (3)

tZX3

IOE output buffer enable delay, slow slew rate = on

C1 = 35 pF (4)

tINREG

IOE input pad and buffer to IOE register delay

tIOFD

IOE register feedback delay

tINCOMB

IOE input pad and buffer to FastTrack Interconnect delay

Table 32. LE Timing Microparameters (Part 2 of 2)

Note (1)

Symbol

Parameter

Conditions

FLEX10KA Datasheet(PDF) 60 Page - Altera Corporation

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