FT800 datasheet(20/55 Pages) FTDI

20 / 55 page

Document No.: FT_000792

FT800

Embedded Video Engine

Datasheet Version 1.1

Clearance No.: FTDI# 334

Figure 4-5 External Clock Input

4.2.2 Phase Locked Loop

The internal PLL takes 12MHz input from the crystal oscillator. The PLL outputs clock to all

internal circuits, including graphics engine, audio engine and touch engine.

4.2.3 Clock Enable

Upon power on the FT800 enters standby mode. The system clock will be enabled when

following steps are executed:

Host sends an “ACTIVE” command (dummy read at address 0)

Host sends an “CLKEXT” command

Host writes to REG_PCLK with non-zero value (ie 5)

If SPI is used as host interface, the SPI clock shall not exceed 11MHz before system clock is

enabled. After system clock is properly enabled, the SPI clock is allowed to go up to 30MHz.

4.2.4 Clock Frequency

By default the system clock is 48MHz. Host is allowed to switch the system clock between

48MHz and 36MHz by the host command “CLK48MHz” and “CLK36MHz” respectively. The clock

switching is synchronised to VSYNC edge on the fly. This is to avoid possible graphics glitch

during clock switching. As a result, the clock switch will only take effect if the REG_PCLK is a

non-zero value.

4.3 Graphics Engine

4.3.1 Introduction

The graphics engine executes the display list once for every horizontal line. It executes the

primitive objects in the display list and constructs the display line buffer. The horizontal pixel

content in the line buffer is updated if the object is visible at the horizontal line.

Main features of the graphics engine are:

FT800 Datasheet(PDF) 20 Page - Future Technology Devices International Ltd.