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FT800 Datasheet(PDF) 25 Page - Future Technology Devices International Ltd. |
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FT800 Datasheet(HTML) 25 Page - Future Technology Devices International Ltd. |
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25 / 55 page ![]() Copyright © 2013 Future Technology Devices International Limited 25 Document No.: FT_000792 FT800 Embedded Video Engine Datasheet Version 1.1 Clearance No.: FTDI# 334 bits per colour in 6:6:6 formats and a 2X2 dither matrix allow the truncated bits to contribute to the final colour values. REG_OUTBITS gives the bit width of each colour channel, the default is 6, 6, 6 bits for each RGB colour. A lower value means fewer bits are output for each channel allowing dithering on lower precision LCD displays. REG_SWIZZLE controls the arrangement of the output colour pins, to help the PCB route different LCD panel arrangements. Bit 0 of the register causes the order of bits in each colour channel to be reversed. Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels to be swapped. Setting Bit 3 allows rotation to be enabled. If Bit 3 is set, then (R,G,B) is rotated right if bit 2 is one, or left if bit 2 is zero. Table 4-10 REG_SWIZZLE RGB Pins Mapping REG_SWIZZLE PINS b3 b2 b1 b0 R7, R6, R5, R4, R3, R2 G7, G6, G5, G4, G3, G2 B7, B6, B5, B4, B3, B2 0 X 0 0 R[7:2] G[7:2] B[7:2] Power on Default 0 X 0 1 R[2:7] G[2:7] B[2:7] 0 X 1 0 B[7:2] G[7:2] R[7:2] 0 X 1 1 B[2:7] G[2:7] R[2:7] 1 0 0 0 G[7:2] B[7:2] R[7:2] 1 0 0 1 G[2:7] B[2:7] R[2:7] 1 0 1 0 G[7:2] R[7:2] B[7:2] 1 0 1 1 G[2:7] R[2:7] B[2:7] 1 1 0 0 B[7:2] R[7:2] G[7:2] 1 1 0 1 B[2:7] R[2:7] G[2:7] 1 1 1 0 R[7:2] B[7:2] G[7:2] 1 1 1 1 R[2:7] B[2:7] G[2:7] |
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