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EP3SL200 Datasheet(PDF) 55 Page - Altera Corporation |
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EP3SL200 Datasheet(HTML) 55 Page - Altera Corporation |
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55 / 341 page  Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–45 I/O Timing © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 3.0-V LVCMOS 4mA GCLK t co 3.046 3.034 4.253 4.610 5.075 4.958 5.157 4.610 5.075 4.958 5.157 ns GCLK PLL tco 3.402 3.402 4.776 5.172 5.685 5.543 5.808 5.172 5.685 5.543 5.808 ns 8mA GCLK t co 2.967 2.955 4.130 4.481 4.940 4.823 5.022 4.481 4.940 4.823 5.022 ns GCLK PLL t co 3.323 3.323 4.652 5.043 5.550 5.408 5.673 5.043 5.550 5.408 5.673 ns 12mA GCLK t co 2.962 2.950 4.122 4.474 4.931 4.813 5.015 4.474 4.931 4.813 5.015 ns GCLK PLL t co 3.318 3.318 4.645 5.036 5.541 5.398 5.665 5.036 5.541 5.398 5.665 ns 16mA GCLK t co 2.953 2.941 4.108 4.459 4.916 4.798 5.000 4.459 4.916 4.798 5.000 ns GCLK PLL t co 3.309 3.309 4.631 5.021 5.526 5.383 5.650 5.021 5.526 5.383 5.650 ns 2.5 V 4mA GCLK t co 3.168 3.156 4.460 4.837 5.322 5.205 5.405 4.837 5.322 5.205 5.405 ns GCLK PLL t co 3.524 3.524 4.983 5.399 5.932 5.790 6.055 5.399 5.932 5.790 6.055 ns 8mA GCLK tco 3.068 3.056 4.341 4.711 5.190 5.073 5.272 4.711 5.190 5.073 5.272 ns GCLK PLL t co 3.424 3.424 4.864 5.273 5.800 5.658 5.923 5.273 5.800 5.658 5.923 ns 12mA GCLK tco 3.024 3.012 4.254 4.620 5.094 4.976 5.178 4.620 5.094 4.976 5.178 ns GCLK PLL t co 3.380 3.380 4.777 5.182 5.704 5.561 5.828 5.182 5.704 5.561 5.828 ns 16mA GCLK t co 2.986 2.974 4.215 4.578 5.051 4.933 5.135 4.578 5.051 4.933 5.135 ns GCLK PLL t co 3.342 3.342 4.738 5.140 5.661 5.518 5.785 5.140 5.661 5.518 5.785 ns Table 1–43. EP3SL50 Column Pins output Timing Parameters (Part 2 of 7) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V |
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