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EP3SL200 Datasheet(PDF) 144 Page - Altera Corporation |
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EP3SL200 Datasheet(HTML) 144 Page - Altera Corporation |
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144 / 341 page  1–134 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation 1.8-V HSTL CLASS I 4mA GCLK tco 3.017 3.249 4.596 5.002 5.481 5.366 5.616 5.099 5.599 5.484 5.692 ns GCLK PLL t co 1.264 1.437 1.829 1.918 2.108 2.134 2.137 2.012 2.208 2.233 2.125 ns 6mA GCLK t co 3.005 3.237 4.587 5.001 5.480 5.365 5.615 5.091 5.599 5.484 5.692 ns GCLK PLL tco 1.257 1.431 1.827 1.917 2.107 2.133 2.136 2.011 2.208 2.233 2.125 ns 8mA GCLK t co 2.992 3.225 4.578 4.994 5.473 5.358 5.608 5.083 5.592 5.477 5.685 ns GCLK PLL t co 1.248 1.423 1.820 1.910 2.100 2.126 2.129 2.004 2.201 2.226 2.118 ns 10mA GCLK t co 2.994 3.227 4.581 4.997 5.477 5.362 5.612 5.086 5.595 5.480 5.688 ns GCLK PLL t co 1.251 1.425 1.823 1.913 2.104 2.130 2.133 2.007 2.204 2.229 2.121 ns 12mA GCLK tco 2.987 3.222 4.579 5.000 5.480 5.365 5.615 5.086 5.600 5.485 5.693 ns GCLK PLL t co 1.247 1.422 1.825 1.916 2.107 2.133 2.136 2.010 2.209 2.234 2.126 ns 1.8-V HSTL CLASS II 16mA GCLK t co 2.993 3.226 4.574 4.997 5.476 5.361 5.611 5.077 5.594 5.479 5.687 ns GCLK PLL t co 1.255 1.430 1.823 1.913 2.103 2.129 2.132 2.006 2.203 2.228 2.120 ns 1.5-V HSTL CLASS I 4mA GCLK t co 3.024 3.256 4.607 5.012 5.492 5.377 5.627 5.111 5.610 5.495 5.703 ns GCLK PLL t co 1.270 1.443 1.838 1.928 2.119 2.145 2.148 2.021 2.219 2.244 2.136 ns 6mA GCLK t co 3.012 3.246 4.603 5.014 5.494 5.379 5.629 5.108 5.613 5.498 5.706 ns GCLK PLL t co 1.264 1.438 1.839 1.930 2.121 2.147 2.150 2.023 2.222 2.247 2.139 ns 8mA GCLK tco 3.008 3.241 4.597 5.009 5.489 5.374 5.624 5.102 5.607 5.492 5.700 ns GCLK PLL t co 1.260 1.434 1.834 1.925 2.116 2.142 2.145 2.018 2.216 2.241 2.133 ns 1.2-V HSTL CLASS I 4mA GCLK t co 3.023 3.255 4.618 5.028 5.511 5.396 5.646 5.125 5.629 5.514 5.722 ns GCLK PLL t co 1.272 1.445 1.851 1.944 2.138 2.164 2.167 2.037 2.238 2.263 2.155 ns 6mA GCLK t co 3.011 3.243 4.607 5.019 5.502 5.387 5.637 5.114 5.620 5.505 5.713 ns GCLK PLL t co 1.263 1.437 1.842 1.935 2.129 2.155 2.158 2.028 2.229 2.254 2.146 ns 8mA GCLK t co 3.007 3.241 4.611 5.027 5.511 5.396 5.646 5.120 5.630 5.515 5.723 ns GCLK PLL t co 1.262 1.437 1.849 1.943 2.138 2.164 2.167 2.037 2.239 2.264 2.156 ns 3.0-V PCI — GCLK tco 3.142 3.376 4.672 5.050 5.535 5.409 5.670 5.171 5.656 5.530 5.749 ns GCLK PLL t co 1.375 1.551 1.897 1.976 2.164 2.185 2.193 2.076 2.267 2.287 2.184 ns 3.0-V PCI-X — GCLK t co 3.142 3.376 4.672 5.050 5.535 5.409 5.670 5.171 5.656 5.530 5.749 ns GCLK PLL t co 1.375 1.551 1.897 1.976 2.164 2.185 2.193 2.076 2.267 2.287 2.184 ns Table 1–74. EP3SL150 Row Pins Output Timing Parameters (Part 4 of 4) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V |
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