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AD9142 Datasheet(PDF) 46 Page - Analog Devices |
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AD9142 Datasheet(HTML) 46 Page - Analog Devices |
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46 / 65 page ![]() AD9142 Data Sheet Rev. 0 | Page 46 of 64 INTERRUPT SELECT1 REGISTER Address: 0x08, Reset: 0x00, Name: IRQ_SEL1 Table 30. Bit Descriptions for IRQ_SEL1 Bits Bit Name Settings Description Reset Access 2 SEL_FIFO_UNDERFLOW 0 Selects the IRQ1 pin. 0x0 RW 1 Selects the IRQ2 pin. 1 SEL_FIFO_OVERFLOW 0 Selects the IRQ1 pin. 0x0 RW 1 Selects the IRQ2 pin. 0 SEL_FIFO_WARNING 0 Selects the IRQ1 pin. 0x0 RW 1 Selects the IRQ2 pin. DAC CLOCK RECEIVER CONTROL REGISTER Address: 0x10, Reset: 0xFF, Name: DACCLK_RECEIVER_CTRL Table 31. Bit Descriptions for DACCLK_RECEIVER_CTRL Bits Bit Name Settings Description Reset Access 7 DACCLK_DUTYCYCLE_CORRECTION Enables duty cycle correction at the DACCLK input. For best performance, the default and recommended status is turned on. 0x1 RW 5 DACCLK_CROSSPOINT_CTRL_ENABLE Enables crosspoint control at the DACCLK input. For best performance, the default and recommended status is turned on. 0x1 RW [4:0] DACCLK_CROSSPOINT_LEVEL A twos complement value. For best performance, it is recommended to set DACCLK_CROSSPOINT_LEVEL to the default value. 0x1F RW 01111 Highest crosspoint. 11111 Lowest crosspoint. REF CLOCK RECEIVER CONTROL REGISTER Address: 0x11, Reset: 0xBF, Name: REFCLK_RECEIVER_CTRL Table 32. Bit Descriptions for REFCLK_RECEIVER_CTRL Bits Bit Name Settings Description Reset Access 7 DUTYCYCLE_CORRECTION Enables duty cycle correction at the REFCLK input. For best performance, the default and recommended status is turned off. 0x0 RW 5 REFCLK_CROSSPOINT_CTRL_ENABLE Enables crosspoint control at the REFCLK input. For best performance, the default and recommended status is turned off. 0x0 RW [4:0] REFCLK_CROSSPOINT_LEVEL A twos complement value. For best performance, it is recommended to set REFCLK_CROSSPOINT_LEVEL to the default value. 0x1F RW 01111 Highest crosspoint. 11111 Lowest crosspoint. |
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