Electronic Components Datasheet Search
  English  ▼

X  

AD9142 Datasheet(PDF) 46 Page - Analog Devices

Part # AD9142
Description  Dual, 16-Bit, 1600 MSPS, TxDAC Digital-to-Analog Converter
PDF  65 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9142 Datasheet(HTML) 46 Page - Analog Devices

Back Button AD9142 Datasheet HTML 42Page - Analog Devices AD9142 Datasheet HTML 43Page - Analog Devices AD9142 Datasheet HTML 44Page - Analog Devices AD9142 Datasheet HTML 45Page - Analog Devices AD9142 Datasheet HTML 46Page - Analog Devices AD9142 Datasheet HTML 47Page - Analog Devices AD9142 Datasheet HTML 48Page - Analog Devices AD9142 Datasheet HTML 49Page - Analog Devices AD9142 Datasheet HTML 50Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 46 / 65 page
background image
AD9142
Data Sheet
Rev. 0 | Page 46 of 64
INTERRUPT SELECT1 REGISTER
Address: 0x08, Reset: 0x00, Name: IRQ_SEL1
Table 30. Bit Descriptions for IRQ_SEL1
Bits
Bit Name
Settings
Description
Reset
Access
2
SEL_FIFO_UNDERFLOW
0
Selects the IRQ1 pin.
0x0
RW
1
Selects the IRQ2 pin.
1
SEL_FIFO_OVERFLOW
0
Selects the IRQ1 pin.
0x0
RW
1
Selects the IRQ2 pin.
0
SEL_FIFO_WARNING
0
Selects the IRQ1 pin.
0x0
RW
1
Selects the IRQ2 pin.
DAC CLOCK RECEIVER CONTROL REGISTER
Address: 0x10, Reset: 0xFF, Name: DACCLK_RECEIVER_CTRL
Table 31. Bit Descriptions for DACCLK_RECEIVER_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
DACCLK_DUTYCYCLE_CORRECTION
Enables duty cycle correction at the DACCLK input. For
best performance, the default and recommended status
is turned on.
0x1
RW
5
DACCLK_CROSSPOINT_CTRL_ENABLE
Enables crosspoint control at the DACCLK input. For best
performance, the default and recommended status is
turned on.
0x1
RW
[4:0]
DACCLK_CROSSPOINT_LEVEL
A twos complement value. For best performance, it is
recommended to set DACCLK_CROSSPOINT_LEVEL to
the default value.
0x1F
RW
01111
Highest crosspoint.
11111
Lowest crosspoint.
REF CLOCK RECEIVER CONTROL REGISTER
Address: 0x11, Reset: 0xBF, Name: REFCLK_RECEIVER_CTRL
Table 32. Bit Descriptions for REFCLK_RECEIVER_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
DUTYCYCLE_CORRECTION
Enables duty cycle correction at the REFCLK input. For
best performance, the default and recommended status
is turned off.
0x0
RW
5
REFCLK_CROSSPOINT_CTRL_ENABLE
Enables crosspoint control at the REFCLK input. For best
performance, the default and recommended status is
turned off.
0x0
RW
[4:0]
REFCLK_CROSSPOINT_LEVEL
A twos complement value. For best performance, it is
recommended to set REFCLK_CROSSPOINT_LEVEL to
the default value.
0x1F
RW
01111
Highest crosspoint.
11111
Lowest crosspoint.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com