AD9142 datasheet(11/65 Pages) AD

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Data Sheet

AD9142

Rev. 0 | Page 11 of 64

Pin No.

Mnemonic

Description

D9N

Data Bit 9, Negative.

D8P

Data Bit 8, Positive.

D8N

Data Bit 8, Negative.

DCIP

Data Clock Input, Positive.

DCIN

Data Clock Input, Negative.

D7P

Data Bit 7, Positive.

D7N

Data Bit 7, Negative.

D6P

Data Bit 6, Positive.

D6N

Data Bit 6, Negative.

D5P

Data Bit 5, Positive.

D5N

Data Bit 5, Negative.

DVDD18

1.8 V Digital Supply. Pin 36 supplies power to the digital core, digital data ports, serial port input/output pins,

RESET, IRQ1, and IRQ2.

D4P

Data Bit 4, Positive.

D4N

Data Bit 4, Negative.

D3P

Data Bit 3, Positive.

D3N

Data Bit 3, Negative.

D2P

Data Bit 2, Positive.

D2N

Data Bit 2, Negative.

DVDD18

1.8 V Digital Supply. Pin 43 supplies power to the digital core, digital data ports, serial port input/output pins,

RESET, IRQ1, and IRQ2.

D1P

Data Bit 1, Positive.

D1N

Data Bit 1, Negative.

D0P

Data Bit 0 (LSB), Positive.

D0N

Data Bit 0 (LSB), Negative.

DVDD18

1.8 V Digital Supply. Pin 48 supplies power to the digital core, digital data ports, serial port input/output pins,

RESET, IRQ1, and IRQ2.

DVDD18

1.8 V Digital Supply. Pin 49 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

IRQ2

Second Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a 10 kΩ resistor.

IRQ1

First Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a 10 kΩ resistor.

SDIO

Serial Port Data Input/Output. CMOS levels with respect to DVDD18.

SCLK

Serial Port Clock Input. CMOS levels with respect to DVDD18.

Serial Port Chip Select. Active low (CMOS levels with respect to DVDD18).

AVDD33

3.3 V Analog Supply.

IOUT2P

QDAC Positive Current Output.

IOUT2N

QDAC Negative Current Output.

AVDD33

3.3 V Analog Supply.

CVDD18

1.8 V Clock Supply. Supplies clock receivers and clock distribution.

CVDD18

1.8 V Clock Supply. Supplies clock receivers and clock distribution.

DACCLKN

DAC Clock Input, Negative.

DACCLKP

DAC Clock Input, Positive.

CVDD18

1.8 V Clock Supply. Supplies clock receivers and clock distribution.

CVDD18

1.8 V Clock Supply. Supplies clock receivers and clock distribution.

AVDD33

3.3 V Analog Supply.

IOUT1N

IDAC Negative Current Output.

IOUT1P

IDAC Positive Current Output.

AVDD33

3.3 V Analog Supply.

FSADJ

Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to AVSS.

REFIO

Voltage Reference. Nominally 1.2 V output. Decouple REFIO to AVSS.

CVDD18

1.8 V Clock Supply. Pin 71 supplies the clock receivers, clock multiplier, and clock distribution.

CVDD18

1.8 V Clock Supply. Pin 72 supplies the clock receivers, clock multiplier, and clock distribution.

EPAD

Exposed Pad. The exposed pad (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an

electrical, thermal, and mechanical connection to the board.

AD9142 Datasheet(PDF) 11 Page - Analog Devices

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