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AD9142 Datasheet(PDF) 52 Page - Analog Devices

Part # AD9142
Description  Dual, 16-Bit, 1600 MSPS, TxDAC Digital-to-Analog Converter
PDF  65 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9142 Datasheet(HTML) 52 Page - Analog Devices

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AD9142
Data Sheet
Rev. 0 | Page 52 of 64
DATA FORMAT SELECT REGISTER
Address: 0x26, Reset: 0x00, Name: DATA_FORMAT_SEL
Table 52. Bit Descriptions for DATA_FORMAT_SEL
Bits
Bit Name
Settings
Description
Reset
Access
7
DATA_FORMAT
Select binary or twos complement data format.
0x0
RW
0
Input data in twos complement format.
1
Input data in binary format.
6
DATA_PAIRING
Indicate I/Q data pairing on data input.
0x0
RW
0
I samples are paired with the next Q samples.
1
I samples are paired with the prior Q samples.
5
DATA_BUS_INVERT
Swap the bit order of the data input port. MSBs become the LSBs:
D[15:0] changes to D[0:15].
0x0
RW
0
The order of the data bits corresponds to the pin descriptions in Table 9.
1
The order of the data bits is inverted.
0
DATA_BUS_WIDTH
Data interface mode. See the LVDS Input Data Ports section for
information about the operation of the different interface modes.
0x0
RW
0
Word mode; 16-bit interface bus width.
1
Byte mode; 8-bit interface bus width.
DATAPATH CONTROL REGISTER
Address: 0x27, Reset: 0x00, Name: DATAPATH_CTRL
Table 53. Bit Descriptions for DATAPATH_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
INVSINC_ENABLE
Enable the inverse sinc filter.
0x0
RW
6
NCO_ENABLE
Enable the NCO.
0x0
RW
5
IQ_GAIN_ADJ_DCOFFSET_ENABLE
Enable digital IQ gain adjustment and dc offset.
0x0
RW
4
IQ_PHASE_ADJ_ENABLE
Enable digital IQ phase adjustment.
0x0
RW
2
FS4_MODULATION_ENABLE
Enable fS/4 modulation function.
0x0
RW
1
NCO_SIDEBAND_SEL
Selects the single-side NCO modulation image.
0x0
RW
0
The NCO outputs the high-side image.
1
The NCO outputs the low-side image.
0
SEND_IDATA_TO_QDAC
Send the IDATA to the QDAC. When enabled, I data is sent
to both the IDAC and the QDAC. The Q data path still runs,
and the Q data is ignored.
0x0
RW
INTERPOLATION CONTROL REGISTER
Address: 0x28, Reset: 0x00, Name: INTERPOLATION_CTRL
Table 54. Bit Descriptions for INTERPOLATION_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
[1:0]
INTERPOLATION_MODE
Interpolation rate and mode selection.
0x0
RW
00
2× Mode 1; use HB1 filter.
10
4× mode; use HB1 and HB2 filters.
11
8× mode; use all three filters (HB1, HB2, and HB3).



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