AD9142 datasheet(57/65 Pages) AD

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Data Sheet

AD9142

Rev. 0 | Page 57 of 64

TX ENABLE CONTROL REGISTER

Address: 0x43, Reset: 0x07, Name: TX_ENABLE_CTRL

Table 77. Bit Descriptions for TX_ENABLE_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

TXENABLE_GAINSTEP_EN

DAC output gradually turns on/off under the control of the

TXENABLE signal from the TXEN pin according to the settings

in Register 0x41 and Register 0x42.

0x1

TXENABLE_SLEEP_EN

When set to 1, the device is put in sleep mode when the

TXENABLE signal from the TXEN pin is low.

0x1

TXENABLE_POWER_DOWN_EN

When set to 1, the device is put in power down mode when

TXENABLE signal from the TXEN pin is low.

0x1

DAC OUTPUT CONTROL REGISTER

Address: 0x44, Reset: 0x8F, Name: DAC_OUTPUT_CTRL

Table 78. Bit Descriptions for DAC_OUTPUT_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

DAC_OUTPUT_CTRL_EN

Enable the DAC output control. This bit needs to be set to 1 to

enable the rest of the bits in this register.

0x1

FIFO_WARNING_SHUTDOWN_EN

When this bit and Bit 7 are both high, if a FIFO warning occurs,

the DAC output shuts down automatically. By default, this

function is on.

0x1

OVERTHRESHOLD_SHUTDOWN_EN

The DAC output is turned off when the input average power is

greater than the predefined threshold.

0x1

FIFO_ERROR_SHUTDOWN_EN

The DAC output is turned off when the FIFO reports warnings.

0x1

DATA RECEIVER TEST CONTROL REGISTER

Address: 0x5E, Reset: 0xFF, Name: DATA_RX_CTRL0

Table 79. Bit Descriptions for DATA_RX_CTRL0

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

DLY_TAP_LSB

See Register 0x5F[2:0].

0xFF

DATA RECEIVER TEST CONTROL REGISTER

Address: 0x5F, Reset: 0x07, Name: DATA_RX_CTRL1

Table 80. Bit Descriptions for DATA_RX_CTRL1

Bits

Bit Name

Settings

Description

Reset

Access

DLYLINE_EN

1 = Enable the data interface.

0x0

[2:0]

DLY_TAP_MSB

Four available delay settings. See the Interface Delay Line section for more

information.

0x7

0x000

0x007

0x07F

0x5FF

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