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APA150 Datasheet(PDF) 171 Page - Actel Corporation |
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APA150 Datasheet(HTML) 171 Page - Actel Corporation |
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171 / 174 page  ProASICPLUS Flash Family FPGAs v5.2 3-5 The following pins have been changed in the "896-Pin FBGA" table: Pin Number Function Pin Number Function R2 I/O (GLMX1) T3 GL2 R4 NPECL1 T4 PPECL1 (I/P) R5 GL1 T26 PPECL2 (I/P) R27 NPECL2 T27 GL4 R29 I/O (GLMX2) T28 GL3 page 2-59 The following pins have been changed in the "1152-Pin FBGA" table: Pin Number Function Pin Number Function U4 I/O (GLMX1) U29 NPECL2 U6 NPECL1 U31 I/O (GLMX2) U7 GL1 V28 PPECL2 (I/P) V5 GL2 V29 GL4 V6 PPECL1 (I/P) V30 GL3 page 2-69 Advanced v0.7 The "ProASICPLUS Architecture" section was updated. page 1-2 The "Array Coordinates" section and Table 1-2 are new. page 1-8 The "Power-Up Sequencing" section is new. page 1-10 "I/O Features" section was updated. page 1-9 The "Timing Control and Characteristics" section was updated. "Physical Implementation" section, "Functional Description" section, "Lock Signal" section, and "PLL Configuration Options" section are new. page 1-13 to page 1-16 "PLL Block – Top-Level View and Detailed PLL Block Diagram" section was updated. page 1-14 Figure 1-15 was updated. page 1-15 "Sample Implementations" section, "Adjustable Clock Delay" section, and the "Clock Skew Minimization" section are new. page 1-16 Figure 1-16, Figure 1-17, Figure 1-18, Figure 1-19, and Figure 1-20 are new. page 1-17 to page 1-19 The "PLL Electrical Specifications" section is new. page 1-21 The "Design Environment" section was updated. page 1-27 Figure 1-26 was updated. page 1-42 The "Calculating Typical Power Dissipation" section was updated. page 1-30 The "DC Electrical Specifications (VDDP = 2.5 V ±0.2V)" section was updated. page 1-36 The Table 1-22 was updated. page 1-38 The "DC Specifications (3.3 V PCI Operation)1" section was updated. page 1-40 The "Tristate Buffer Delays" section (the figure and table) have been updated. page 1-42 The "Output Buffer Delays" section (the figure and table) have been updated. page 1-44 The "Input Buffer Delays" section was updated. page 1-46 The "Global Input Buffer Delays" section was updated. page 1-48 The "Predicted Global Routing Delay" section was updated. page 1-50 The "Global Routing Skew" section was updated. page 1-50 The "Sample Macrocell Library Listing" section was updated. page 1-51 The "Pin Description" section was updated. GLMX is new. page 1-73 The "Recommended Design Practice for VPN/VPP" section was updated. page 1-74 Pin AK31 of FG1152 for the APA1000 changed to VPP. page 2-69 (Advanced v0.6) The "Features and Benefits" on page i-i were updated. page i-i The "ProASICPLUS Product Profile" on page i-i was updated. page i-i The "Ordering Information" on page i-ii was updated. page i-ii The "Plastic Device Resources" on page i-ii was updated. page i-ii The "ProASICPLUS Architecture" on page 1-2 was updated. page 1-2 Previous version Changes in current version (v5.2) Page |
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