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Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Not

Used

Bit 7

Bit 6

MSB

LSB

GPIO Register

NTC

External

Flag

Data

Direction

Data

Direction

TX1/TORCH/

GPIO1

ENVM/

TX2/GPIO2

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

N/A

Bit 7

Bit 6

MSB

LSB

Configuration Register 2

N/A

AET

Mode

NTC

Shutdown

TX2

Shutdown

VIN Monitor

Mode

N/A

LM3554

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SNVS549A – JUNE 2009 – REVISED APRIL 2011

CONFIGURATION REGISTER 2

Configuration Register 2 contains the bits to select if TX2, NTC, and the VIN monitor force Torch mode or force

the Flash LEDs into shutdown. Additionally, bit [2] (AET bit) selects the Alternate External Torch mode (see

Figure 24 and Table 7).

Figure 24. Configuration Register 2 Description

Table 7. Configuration Register 2 Bit Settings

Bit 7 (Not

Bit 6 (Not

Bit 5 (Not

Bit 4 (Not

Bit 3 (VIN

Bit 2 (AET

Bit 1

Bit 0

used)

Monitor

mode)

(NTC

(TX2

Shutdown)

Reads Back '1'

0 = If IN drops

0 = Normal

0 = LEDI/NTC

0 = TX2 event

below the

operation for

pin going below

forces the

programmed

TX1/TORCH

VTRIP forces the

LEDs into

threshold and

high before

LEDs into

Torch mode

the VIN Monitor

STROBE (TX1

Torch mode

(TX2 mode

feature is

mode only)

(NTC mode

only) default

enabled, the

default

only) default

LED's are

forced into

Torch mode

(default)

1 = If IN drops

1 = Alternative

1 = LEDI/NTC

1 = TX2 event

below the

External Torch

pin going below

forces the

programmed

operation.

VTRIP forces the

LEDs into

threshold and

TX1/TORCH

LEDs into

shutdown (TX2

the VIN Monitor

high before

shutdown (NTC

mode only)

feature is

STROBE

mode only)

enabled, the

forces Torch

LED's turn off

mode with no

timeout (TX1

mode only)

GPIO REGISTER

The GPIO register contains the control bits which change the state of the TX1/TORCH/GPIO1 pin and the

ENVM/TX2/GPIO2 pin to general purpose I/O’s (GPIO’s). Additionally, bit[6] of this register configures the

ENVM/TX2/GPIO2 as a hardware interrupt output reflecting the NTC flag bit in the Flags Register. Figure 25 and

Table 8 describe the bit description and functionality of the GPIO register.

Figure 25. GPIO Register Description

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