ML7344J datasheet(118/151 Pages) ETC2

118 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

118/151

(4) ACK transmission

ACK TX flow is as follows. During RX, ACK frame can be set in the TX FIFO.

Yes

Write TX data *4

[WR_TX_FIFO:B0 0x7C]

Yes

From RX flow

Yes

CRC error (INT[9])?

[INT_SOURCE_GRP2] B0 0x0E(1)]

TX_ON issue *6

[RF_STATUS: B0 0x0B]

TRX_OFF issue

[RF_STATUS: B0 0x0B]

Read all RX data

[RD_FIFO:B0 0x7F]

Clear TX FIFO pointer

[STATE_CLR: B0 0x16(0)]

*4 ACK frame is set to TX FIFO.

Yes

Clear RX FIFO pointer

[STATE_CLR: B0 0x16(1)]

*6 Please refer to RF state

transition wait flow.

START

Read RX data *3

[RD_FIFO:B0 0x7F]

Yes

RX FIFO trigger setting *1

[RXFIFO_THRH: B0 0x19]

[RXFIFO_THRL: B0 0x1A]

RX_ON issue*2

[RF_STATUS: B0 0x0B]

* In case of using interrupt,

FIFO-Full interrupt notification should be ON.

*3 read address field to

check length and

packet destination.

*2 Please refer to RF state transition wait

flow.

FIFO-Full interrupt?

INT[5] [INT_SOURCE_GRP1: B0 0x0D]

Self addressed?

RX completion (INT[8])? *5

[INT_SOURCE_GRP2: B0 0x0E(0)]

TX completion (INT[16])?

[INT_SOURCE_GRP3] B0 0x0F(0)]

INT[8] and [9] clear

[INT_SOURCE_GRP2: B0 0x0E]

Read RX data?

END

*5 Please refer the following

“NOTE”

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