ML7344J datasheet(119/151 Pages) ETC2

119 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

119/151

NOTE:

If setting “FAST_TX_EB=0b1” or “AUTO_TX_EN=0b1 or “RXDONE_MODE[1:0]=0b01 (move to TX

state)” at the [RF_STATUS:CTRL:B0 0x0A] register, moving to TX_ON state automatically after RX

completion in above flowchart.

Even if CRC error occurs, moving to TX_ON state. Since CRC errors interrupt (INT[9] group2) and RX

completion interrupt (INT[8] group2) occur almost same timeing, Therefore in case of CRC error interrupt

occurs, Force_TRX_OFF should be issued by [RF_STATUS:B0 0x0B] register withing the transition time from

RX state to TX state(1.188msec), and clear TX FIFO pointer by [STATE_CLR:B0 0x16] register. When it is

hard to issue Force_TRX_OFF during the trasition time due to MCU performance, “FAST_TX”, “AUTO_TX”

and “move to TX state after RX completion” should be disabled. (In “FAST_TX”, trnasmitting conditoin

depends on [TXFIFO_THRL:B0 0x18] register.)

(5) Field check transmission

After enabling Filedcheck functions, issuing RX_ON by [RF_STATUS:B0 0x0B] register. According to the

setting of CA_INT_CTRL([C_CHECK_CTRL:B0 0x1B(6)]), filed checking result (match or no match) can be

notified by the INT[14](group2: Field checking interrupt). Numbers of unmatched packets can be counted and

stored into [ADDR_CHK_CTR_H/L: B1 0x62/0x63]) registers. This counter can be cleared by STATE_CLR4

[STATE_CLR: B0 0x16(4)](Address check counter clear).

START

RX_ON issue

[RF_STATUS] B0 0x0B]

Field check setting *1

RX flow

Yes

Read RX data?

Field checking compete (INT[14])?

[INT_SOURCE_GRP2] B0 0x0E(6)]

Yes

INT[14] clear

[INT SOURCE GRP2: B0

Yes

INT GRP2 clear *2

[INT_SOURCE_GRP2: B0 0x0E]

*1 C-field/M-field/A-field check can be possible with

the setting below.

[C_CHECK_CTRL: B0 0x1B]

[M_CHECK_CTRL: B0 0x1C]

[A_CHECK_CTRL: B0 0x1D]

[C_FIELD_WORD1-5: B0 0x1E-0x22]

[M_FIELD_WORD1-4: B0 0x21-0x26]

[A_FIELD_WORD1-6: B0 0x27-0x2C]

Yes

RX completion (INT[8])?

[INT_SOURCE_GRP2] B0 0x0E(0)]

*2 Clear all remaining interrupt

in the group 2.

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