Mne-

Ope-

Operation Code

Operation

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monic

rands

B1

B2

Condition

Transfers the contents of the accumulator

←A

to the four high-order bits of the shift

TAMSIO

001111110

0111110

←(HL)

register and the contents of the memory

addressed by HL to the four low-order bits.

Transfers the four high-order bits of the

TSIOAM

001111110

0111010

A

shift register to the accumulator and the

(HL)

four low-order bits to the memory

addressed by HL.

SIO

001111110

0110011

Start SIO

Starts shifting.

TIMER

001111110

0110010

Start Timer

Starts timer operation.

Transfers the four high-order bits of

A

the count register to the accumulator

TCNTAM

001111110

0111011

(HL)

and the four low-order bits to the

memory addressed by HL.

IPL

01110000

A

←Port (L)

Loads the contents of the port specified

by the L register to the accumulator.

Outputs the contents of the accumu-

OPL

01110010

Port/Mode reg. (L)

←A

lator to the port specified by the L

register or the mode register.

RPBL*

01011100

Port bit (L)

←0

Resets the bits of ports 8, 10, and 11,

that are specified by the L register.

SPBL*

01011101

Port bit (L)

←1

Sets the bits of ports 8, 10, and 11,

that are specified by the L register.

HALT

001111110

0110110

Set Halt Mode

Sets the HALT mode.

STOP

001111110

0110111

Set Stop Mode

Sets the STOP mode.

NOP

00000000

No operation

Performs no operation for one

machine cycle.

Note

*

SPBL and RPBL are bit-wise set/reset instructions. They perform output to each 4-bit port including the specified bits as well as set and reset operation

(They output the contents of the output latch to bits other than the specified bits.). Before executing these instructions, intialize the contents of the output

latch using the OPL instruction.

Note

Instruction Group