UPD7564 datasheet(11/56 Pages) NEC

11 / 56 page

µPD7564A, 7564A(A)

1.6

RECOMMENDED CONNECTION OF UNUSED

µPD7564A PINS

Recommended Connection

P00/INT0

Connect to VSS.

P01 to P03

Connect to VSS or VDD.

P80 to P82

Leave open.

P100 to P103

P110 to P113

1.7

OPERATION OF INPUT/OUTPUT PORTS

(1) P00 to P03 (Port 0)

The port 0 is a 4-bit input port consisting of 4-bit input pins P00 to P03. In addition to being used for port input,

P00 serves as a count clock input or testable input (INT0), each of P01 to P03 serves as a serial interface input/output.

To use P00 as a count clock input, set bits 2 (CM2) and 1 (CM1) of the clock mode register to 01. (See 2.10 “CLOCK

CONTROL CIRCUIT” for details.)

To use P00 as a INT0, set bit 3 (SM3) of the shift mode register to 1.

The serial interface function to use P01 to P03 as a serial interface I/O port is determined by bits 2 and 1 (SM2

and SM1) of the shift mode register. See 2.12 “SERIAL INTERFACE” for details.

Even though this port operates using any function other than the port function, execution of the port input

instruction (IPL) permits loading data on the P00 to P03 line to the accumulator (A0 to A3) at any time.

(2) P80 to P83 (Port 8)

The port 8 is a 4-bit output port with an output latch, which consists of 4-bit output pin.

The port output instruction (OPL) latches the content of the accumulator (A0 to A3) to the output latch and outputs

it to pins P80 to P83.

The SPBL and RPBL instructions allow bit-by-bit setting and resetting of pins P80 to P82.

For these ports, mask options for the output format are available to select CMOS (push-pull) output or N-ch open-

drain output.

The port specified as a N-ch open-drain output and provides an efficient interface to the circuit operating at a

different supply voltage because the output buffer has a dielectric strength of 9 V.

Input state : Connect to VSS or VDD.

Output state: Leave open.

UPD7564 Datasheet(PDF) 11 Page - NEC