UPD7564 datasheet(23/56 Pages) NEC

23 / 56 page

µPD7564A, 7564A(A)

Fig. 2-16 Shift Mode Register Format

Shift Mode Register

Settings for serial interface operation and the associated mode of the port 0

INT0/INTS selection

SM3

Test Sources

INTS

INT0

Caution

When setting a code in the shift mode register using the OPL instruction, be sure to set bit 0 of the

accumulator to 0 (Bit 0 corresponds to CM0 of the

µPD7500H of EVAKIT-7500B in emulation).

In the system which does not require serial interface, the 8-bit shift register can be used as a simple register and

data can be read or writtene by the TSIOAM or TAMSIO instruction when serial operation is off.

2.13 TEST CONTROL CIRCUIT

The

µPD7564A is provided with the following three types of test sources (one external source and two internal

sources):

The test control circuit checks consist mainly of test request flags (INTT RQF and INT0/S RQF) which are set by

three different test sources and the test request flag control circuit which checks the content of test request flags

using the SKI instruction and controls resetting the checked flags.

The INT0 and INTS are common in the request flag. Which one is selected is determined by bit 3 (SM3) of the

shift mode register.

SM3

SM2

SM1

SM2

SM1

P03/SI

P02/SO

P01/SCK

Serial Operation

Port input

Stop

φ continuous output

SI input

SO output

SCK input

Operation based on external clock

SCK output (

φ × 8)

Operation based on

Test Sources

Internal/External

Request Flag

INTT (Overflow from timer/event counter)

Internal

INTT RQF

INT0 (Test request signal from P00 pin)

External

INT 0/S RQF

INTS (Transfer end signal from serial interface)

Internal

SM3

Test Sources

INTS

INT0

UPD7564 Datasheet(PDF) 23 Page - NEC

UPD7564 Datasheet(HTML) 23 Page - NEC

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