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UPD7564 Datasheet(PDF) 7 Page - NEC |
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UPD7564 Datasheet(HTML) 7 Page - NEC |
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7 / 56 page  7 µPD7564A, 7564A(A) 1.3 PIN MASK OPTION Each pin is provided with the following mask options which can be selected for each bit according to the purpose: Pin Name Mask Options P00 No internally provided resistor Pull-down resistor internally provided Pull-up resistor internally provided P01 No internally provided resistor Pull-down resistor internally provided Pull-up resistor internally provided P02 No internally provided resistor Pull-down resistor internally provided Pull-up resistor internally provided P03 No internally provided resistor Pull-down resistor internally provided Pull-up resistor internally provided P80 N-ch open-drain output CMOS (push-pull) output P81 N-ch open-drain output CMOS (push-pull) output P82 N-ch open-drain output CMOS (push-pull) output P100 N-ch open-drain input/output Push-pull input/output N-ch open-drain + pull-up resistor built-in input/output P101 N-ch open-drain input/output Push-pull input/output N-ch open-drain + pull-up resistor built-in input/output P102 N-ch open-drain input/output Push-pull input/output N-ch open-drain + pull-up resistor built-in input/output P103 N-ch open-drain input/output Push-pull input/output N-ch open-drain + pull-up resistor built-in input/output P110 N-ch open-drain input/output Push-pull input/output N-ch open-drain + pull-up resistor built-in input/output P111 N-ch open-drain input/output Push-pull input/output N-ch open-drain + pull-up resistor built-in input/output P112 N-ch open-drain input/output Push-pull input/output N-ch open-drain + pull-up resistor built-in input/output P113 N-ch open-drain input/output Push-pull input/output N-ch open-drain + pull-up resistor built-in input/output RESET Incorporating no pull-down resistor Incorporating a pull-down resistor There is no mask option for PROM products. For more information, see the µPD75P64 Data Sheet (IC-2838). 1.4 CAUTION ON USE OF P00/INT0 PIN AND RESET PIN In addition to the functions shown in 1.1, 1.2 and 1.3, the P00/INT0 pin and RESET pin have a function for setting the test mode in which the internal operation of the µPD7564A is tested (IC test only). When a potential greater than VSS is applied to either of these pins, the test mode is set. As a result, if noise exceeding VSS is applied during normal operation, the test mode will be entered and normal operation may be impeded. If, for example, the routing of the wiring between the P00/INT0 pin and RESET pin is long, the above problem may occur as the result of inter-wiring noise between these pins. Therefore, wiring should be carried out so as to suppress inter-wiring noise as far as possible. If it is not possible to suppress noise, anti-noise measures should be taken using external parts as shown in the figures below. • Connection of diode with small VF between P00/ INT4/RESET pin and VSS • Connection of capacitor between P00/INT0/ RESET pin and VSS VDD VDD P00/INT0, RESET VSS VDD VDD P00/INT0, RESET VSS Diode with Small VF 5 |
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