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UPD7564 Datasheet(PDF) 19 Page - NEC |
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UPD7564 Datasheet(HTML) 19 Page - NEC |
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19 / 56 page  19 µPD7564A, 7564A(A) 2.10 CLOCK CONTROL CIRCUIT The clock control circuit consists of 2-bit clock mode registers (CM2 and CM1), prescalers 1, 2 and 3, and a multiplexer. The circuit inputs the system clock generator output (CL) and the event pulse (P00). It also selects a clock source and a prescaler according to the specifications of clock mode register and supplies a count pulse (CP) to the timer/event counter. Fig. 2-10 Clock Control Circuit CP CL P00 PRESCALER 1 (1/4) PRESCALER 2 (1/8) PRESCALER 3 (1/8) OPL* CM2 CM1 Internal Bus * Instruction execution Use the OPL instruction to set codes in the clock mode registers. Fig. 2-11 Clock Mode Register Format Clock Mode Register Caution When setting codes in the clock mode registers using the OPL instruction, be sure to set bit 0 of the accumulator to 0. (Bit 0 corresponds to CM0 of the µPD7500 of EVAKIT-7500B in emulation.) CM2 CM1 CM2 CM1 Count Pulse Frequency (CP) 0 0 CL × 1 256 0 1 P00 1 0 CL × 1 32 1 1 CL × 1 4 |
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