AS260 datasheet(18/45 Pages) ONSEMI

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AR0260 DS Rev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor

Image Data Output Interface

Figure 12:

Pixel Data Timing Example

Note:

Shown is 10-bit Bayer data in 8 + 2 mode.

Figure 13:

Row Timing, FV, and LV Signals

Notes:

1. P: Frame start and end blanking time.

2. A: Active data time.

3. Q: Horizontal blanking time.

MIPI Port

The MIPI output implements a serial differential sub-LVDS transmitter capable of up to

1536 Mbps (768 Mbps/lane). It supports multiple formats, error checking, and custom

short packets.

When the sensor is in the hardware standby system state or in the software standby

system state, the MIPI signals (CLK_P, CLK_N, DATA_P, DATA_N, DATA_2P, DATA_2N)

indicate ultra low power state (ULPS) corresponding to (nominal) 0V levels being driven

on CLK_P, CLK_N, DATA_P, DATA_N, DATA_2P, and DATA_2N. This is equivalent to

signaling code LP-00.

When the sensor enters the streaming system state, the interface goes through the

following transitions:

1. After the PLL has locked and the bias generator for the MIPI drivers has stabilized, the

MIPI interface transitions from the ULPS state to the ULPS-exit state (signaling code

LP–10).

2. After a delay (TWAKEUP), the MIPI interface transitions from the ULPS-exit state to the

TX-stop state (signaling code LP–11).

3. After a short period of time (the programmed integration time plus a fixed overhead),

frames of pixel data start to be transmitted on the MIPI interface. Each frame of pixel

data is transmitted as a number of high-speed packets. The transition from the

TX-stop state to the high-speed signaling states occurs in accordance with the MIPI

specifications. Between high-speed packets and between frames, the MIPI interface

idles in the TX-stop state. The transition from the high-speed signaling states and the

TX-stop state takes place in accordance with the MIPI specifications.

P0 (9:2)

P0 (1:0)

P1 (9:2)

P1 (1:0)

P2 (9:2)

Pn-1 (9:2)

Pn (9:2)

LINE_VALID

PIXCLK

DOUT[7:0]

Blanking

Valid Data

Pn-1 (1:0)

Pn (1:0)

FRAME_VALID

LINE_VALID

Data Modes

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