AS260 datasheet(42/45 Pages) ONSEMI

42 / 45 page

AR0260 DS Rev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor

Electrical Specifications

Figure 31:

Parallel Pixel Bus Timing Diagram

Notes:

1. FRAME_VALID leads LINE_VALID by 6 PIXCLKs.

2. FRAME_VALID trails LINE_VALID by 6 PIXCLKs.

3. DOUT[7:0], FRAME_VALID, and LINE_VALID are shown with respect to the rising edge of PIXCLK. This

feature is programmable and DOUT[7:0], FRAME_VALID, and LINE_VALID can be synchronized to the

falling edge of PIXCLK.

Table 26:

Two-Wire Serial Interface Timing Data

fEXTCLK = 24 MHz; REG_IN0 = 1.8V; VDD_IO = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; T

J = 70°C; CLOAD = 68.5pF

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCLK

Serial interface input clock

frequency

100

–

400

kHz

tSCLK

Serial interface input clock period

2.5

–

s

SCLK duty cycle

SCLK/SDATA rise time

–

300

tSRTS

Start setup time

Master write to slave

600

–

tSRTH

Start hold time

Master write to slave

300

–

tSDH

SDATA hold

Master write to slave

300

–

tSDS

SDATA setup

Master write to slave

300

–

tSHAW

SDATA hold to ack

Master read from slave

150

–

tAHSW

Ack hold to SDATA

Master read from slave

150

–

tSTPS

Stop setup time

Master write to slave

300

–

tSTPH

Stop hold time

Master write to slave

600

–

tSHAR

SDATA hold to ack

Master write to slave

300

–

tAHSR

Ack hold to SDATA

Master write to slave

300

–

tSDHR

SDATA hold

Master read from slave

300

–

tSDSR

SDATA setup

Master read from slave

350

–

PIXCLK

FRAME_VALID,

LINE_VALID

tPFL

tPLL

tPFH

tPLH

tPD

DOUT[7:0]

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