AS260 datasheet(29/45 Pages) ONSEMI

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AR0260 DS Rev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor

Camera Control and Auto Functions

General Purpose I/Os

The three general purpose I/Os (GPIOs) of the AR0260 can be configured in multiple

ways. Each of the I/Os can be used for multiple purposes and can be programmed from

the host. The GPIOs are powered by their own power supply.

Hardware Functions

Two-Wire Serial Interface

The two-wire serial interface bus enables read and write access to control and status

registers and variables within the AR0260.

The interface protocol uses a master/slave model in which a master controls one or

more slave devices. The AR0260 always operates in slave mode. The host (master) gener-

ates a clock (SCLK) that is an input to the AR0260 and is used to synchronize transfers.

Data is transferred between the master and the slave on a bidirectional signal (SDATA).

Protocol

Data transfers on the two-wire serial interface bus are performed by a sequence of low-

level protocol elements, as follows:

1. a (repeated) start condition

2. a slave address/data direction byte

3. a 16-bit register address (8-bit addresses are not supported)

4. an (a no) acknowledge bit

5. a 16-bit data transfer (8-bit data transfers are not supported)

6. a stop condition

The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a

start condition, and the bus is released with a stop condition. Only the master can

generate the start and stop conditions.

A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.

At the end of a transfer, the master can generate a start condition without previously

generating a stop condition; this is known as a repeated start or restart condition.

A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.

Data is transferred serially, 8 bits at a time, with the most significant bit (MSB) trans-

mitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit.

This data transfer mechanism is used for the slave address/data direction byte and for

message bytes. One data bit is transferred during each SCLK clock period. SDATA can

change when SCLK is LOW and must be stable while SCLK is HIGH.

Slave Address

Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data

transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. If the

SADDR signal is driven LOW, then addresses used by the AR0260 are R0x090 (write

address) and R0x091 (read address). If the SADDR signal is driven HIGH, then addresses

used by the AR0260 are R0x0BA (write address) and R0x0BB (read address).

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