LM5045 datasheet(16/46 Pages) TI

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Hiccup Mode off-time

Soft-Start

Restart delay

Count to Eight

LM5045

SNVS699H – FEBRUARY 2011 – REVISED JANUARY 2015

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Feature Description (continued)

Figure 10. Hiccup Mode Delay and Soft-Start Timing Diagram

7.3.8 PWM Comparator

The LM5045 pulse width modulator (PWM) comparator is a three input device, it compares the signal at the

RAMP pin to the loop error signal or the soft-start, whichever is lower, to control the duty cycle. This comparator

is optimized for speed to achieve minimum controllable duty cycles. The loop error signal is received from the

external feedback and isolation circuit in the form of a control current into the COMP pin. The COMP pin current

is internally mirrored by a matching pair of NPN transistors which sink current through a 5-k

Ω resistor connected

to the 5-V reference. The resulting control voltage passes through a 1-V offset, followed by a 2:1 resistor divider

before being applied to the PWM comparator.

An optocoupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is

controlled by a current input, the potential difference across the optocoupler detector is nearly constant. The

bandwidth limiting phase delay which is normally introduced by the significant capacitance of the optocoupler is

thereby greatly reduced. Higher loop bandwidths can be realized because the bandwidth limiting pole associated

with the optocoupler is now at a much higher frequency. The PWM comparator polarity is configured such that

with no current flowing into the COMP pin, the controller produces maximum duty cycle.

7.3.9 Ramp Pin

The voltage at the RAMP pin provides the modulation ramp for the PWM comparator. The PWM comparator

compares the modulation ramp signal at the RAMP pin to the loop error signal to control the duty cycle. The

modulation ramp signal can be implemented either as a ramp proportional to the input voltage, known as feed-

forward voltage mode control, or as a ramp proportional to the primary current, known as current mode control.

The RAMP pin is reset by an internal MOSFET with an RDS(ON) of 5.5 Ω at the conclusion of each PWM cycle.

The ability to configure the RAMP pin for either voltage mode or current mode allows the controller to be

implemented for the optimum control method depending upon the design constraints. Refer to the Application

and Implementation section for more details on configuring the RAMP pin for feed-forward voltage mode control

and peak current mode control.

7.3.10 Slope Pin

For duty cycles greater than 50% (25% for each phase), peak current mode control is subject to sub-harmonic

oscillation. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow duty

cycles. This can be eliminated by adding an artificial ramp, known as slope compensation, to the modulating

signal at the RAMP pin. The SLOPE pin provides a current source ramping from 0 to 100

μA, at the frequency set

by the RT resistor, for slope compensation. The ramping current source at the SLOPE pin can be used in several

different ways to add slope compensation to the RAMP signal:

•

As shown in Figure 11(a), the SLOPE and RAMP pins can be connected together through an appropriate

resistor to the CS pin. This configuration will inject current sense signal plus slope compensation to the RAMP

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