LM5045 datasheet(20/46 Pages) TI

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HO1/LO2

HO2/LO1

SR1

SR2

Waveforms during soft-start

Waveforms after soft-start

CLK

Freewheel

Power

Transfer

LM5045

SNVS699H – FEBRUARY 2011 – REVISED JANUARY 2015

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Feature Description (continued)

freewheeling cycle. At the end of the freewheel cycle, that is, at the rising edge of the internal CLK, the SR FET

in-phase with the next power transfer cycle is kept on while the SR FET out of phase with it is turned-off. The in-

phase SR FET is kept on throughout the power transfer cycle and at the end of it, both the primary FETs and the

in-phase SR FETs are turned-off together. The synchronous rectifier outputs can be disabled by grounding the

SSSR pin.

Waveforms during Soft-Start

Waveforms after Soft-Start

Figure 14. Waveforms

7.3.15 Prebias Startup

A common requirement for power converters is to have a monotonic output voltage start-up into a prebiased load

such as a precharged output capacitor. In a prebiased load condition, if the synchronous rectifiers are engaged

prematurely they will sink current from the precharged output capacitors resulting in an undesired output voltage

dip. This condition is undesirable and could potentially damage the power converter. The LM5045 uses unique

control circuitry to ensure intelligent turnon of the synchronous rectifiers such that the output has a monotonic

start-up. Initially, the SSSR capacitor is held at ground to disable the synchronous MOSFETs allowing the body

diode to conduct. The synchronous rectifier soft-start is initiated once it is established the duty cycle is controlled

by the COMP instead of the soft-start capacitor, that is, ICOMP < 800 µA and the voltage at the SS pin > 2 V. The

SSSR capacitor is then released and is charged by a 20-µA current source. Further, as shown in Figure 15, a 1-

V offset on the SSSR pin is used to provide additional delay. This delay ensures the output voltage is in

regulation avoiding any reverse current when the synchronous MOSFETs are engaged.

7.3.16 Soft-Stop

As shown in Figure 16, if the UVLO pin voltage falls below the 1.25-V standby threshold, but above the 0.4-V

shutdown threshold, the SSSR capacitor is soft-stopped with a 60-µA current source (3 times the charging

current). Once the SSSR pin reaches the 1.0-V threshold, both the SS and SSSR pins are immediately

discharged to GND. Soft-stopping the power converter gradually winds down the energy in the output capacitors

and results in a monotonic decay of the output voltage. During the hiccup mode, the same sequence is executed

except that the SSSR is discharged with a 120-µA current source (6 times the charging current). In case of an

OVP, VCC UV, thermal limit or a VREF UV condition, the power converter hard-stops, whereby all of the control

outputs are driven to a low state immediately.

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