MT9196

Preliminary Information

7-136

IDPC. During a valid read transfer from IDPC data

simultaneously clocked out by the micro is ignored

by IDPC.

All data transfers through the microport are two-byte

transfers requiring the transmission of a Command/

Address byte followed by the data byte written or

read from the addressed register. CS must remain

asserted for the duration of this two-byte transfer. As

shown in Figures 5 and 6 the falling edge of CS

indicates to the IDPC that a microport transfer is

about to begin. The first 8 clock cycles of SCLK after

the falling edge of CS are always used to receive the

Command/Address byte from the microcontroller.

The Command/Address byte contains information

detailing whether the second byte transfer will be a

read or a write operation and at what address. The

next 8 clock cycles are used to transfer the data byte

Figure 5 - Serial Port Relative Timing for Intel Mode 0

Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire

XX

R/W

Œ

Delays due to internal processor timing which are transparent to IDPC.

y

The IDPC:- latches received data on the rising edge of SCLK.

Ž

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The



A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.



The COMMAND/ADDRESS byte contains:

Œ

Ž





Œ

y

Ž



COMMAND/ADDRESS

DATA INPUT/OUTPUT

COMMAND/ADDRESS:

DATA 1

RECEIVE

DATA 1

TRANSMIT

SCLK

CS

- outputs transmit data on the falling edge of SCLK.

subsequent byte is always data until terminated via CS returning high.

1 bit - Read/Write

5 bits - Addressing Data

2 bits - Unused

Œ

Ž



Œ

y

Ž



COMMAND/ADDRESS

DATA INPUT/OUTPUT

COMMAND/ADDRESS:

DATA 2

RECEIVE

DATA 1

TRANSMIT

SCLK

CS

R/W

X

Œ

Delays due to internal processor timing which are transparent to IDPC.

y

The IDPC:- latches received data on the rising edge of SCLK.

Ž

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The



A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.



The COMMAND/ADDRESS byte contains:

- outputs transmit data on the falling edge of SCLK.

subsequent byte is always data until terminated via CS returning high.

1 bit - Read/Write

5 bits - Addressing Data

2 bits - Unused

