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MT9196AS Datasheet(PDF) 7 Page - Mitel Networks Corporation

Part # MT9196AS
Description  ISO2-CMOS Integrated Digital Phone Circuit (IDPC)
PDF  38 Pages
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Manufacturer  MITEL [Mitel Networks Corporation]
Direct Link  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

MT9196AS Datasheet(HTML) 7 Page - Mitel Networks Corporation

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Preliminary Information
MT9196
7-133
Low and high tones are enabled individually via the
LoEn and HiEN control bits (DTMF/Ringer Control
Register, address 18h). This not only provides
control over dual tone generation but also allows
single tone generation using either of the enable bits
and its associated coefficient register.
After programming and enabling the tone generators
as described, selection of transmit and/or receive
path destinations are carried out via the Path Control
Registers (see Path Control section). In addition
receive sidetone DTMF must be selected via the
DTMF StEN bit (DTMF/Tone ringer Register, address
18h) so that it replaces the received PCM in the Rx
Filter path.
Table 2 - DTMF Frequencies
DTMF Signal to distortion:
The sum of harmonic and noise power in the frequency band
from 50 Hz to 3500 Hz is typically more than 30 dB below the
power in the tone pair. All individual harmonics are typically
more than 40 dB below the level of the low group tone.
Table 2 gives the standard DTMF frequencies, the
coefficient
required
to
generate
the
closest
frequency, the actual frequency generated and the
percent deviation of the generated tone from the
nominal.
Tone Ringer
A dual frequency squarewave ringing signal may be
applied to the handsfree speaker driver to generate a
call alerting signal. To enable this mode the Ring En
bit (address 18h) must be set as well as the ringer
function to the loudspeaker via the Receive Path
Control
Register
(address
13h).
Ring
En
is
independent of the DTMF enable control bits (see Lo
EN and Hi EN). Since both functions use the same
coefficient registers they are not usually enabled
simultaneously.
The
digital
tone
generator
uses
the
values
programmed into the low and high Tone Coefficient
Registers (addresses 1Ah and 1Bh) to generate two
different squarewave frequencies.
Frequency
(Hz)
COEFF
Actual
Frequency
%
Deviation
697
59h
695.3
-.20%
770
63h
773.4
+.40%
852
6Dh
851.6
-.05%
941
79h
945.3
+.46%
1209
9Bh
1210.9
+.20%
1336
ABh
1335.9
.00%
1477
BDh
1476.6
-.03%
1633
D1h
1632.8
-.01%
Both coefficients are determined by the following
equation:
COEFF = [32000/Frequency (Hz)] - 1
where COEFF is an integer between 1 and 255. This
produces frequencies between 125 - 16000 Hz with
a non-linear resolution.
The ringer program switches between these two
frequencies at a 5 Hz or 10 Hz rate as selected by
the WR bit in the DTMF/Tone ringer register (address
18h).
Anti-Howl
IDPC includes an Anti-Howling circuit plus speaker
gain control circuit to allow for group listening
operation. Although this is the main function of the
circuit there are additional modes in which it may be
used as defined by the MS1 and MS0 control bits
(address 1Ch).
MS1
MS0
Operational Mode
0
0
Tx noise reduction (squelch)
0
1
Rx noise reduction (squelch)
1
0
switched loss group listening
(anti-howling)
1
1
Tx/Rx switched loss
The circuit is enabled by setting the Anti-howl Enable
bit
(address
1Ch)
and
selecting
the
required
operational mode (MS0 & MS1) as described.
For all modes of operation the switching levels and
inserted loss are programmed as follows.
Switching decisions are made by comparing either
the transmit or the receive signal level to threshold
levels
stored
in
the
High
Threshold
Register
(address 1Dh) and the Low Threshold Register
(address 1Eh). Threshold data is encoded in PCM
sign-magnitude format excluding the sign bit. For
example; THh0 - THh3 encode the PCM step
number while THh4 - THh6 encode the PCM chord
number for the high threshold. Similarily for the THl0
- THl6 bits of the low threshold. The difference
between the high and low threshold levels provides
the circuit with hysteresis to prevent uncontrolled
operation. The low level threshold must never be
programmed to a value higher than the one stored in
the high level threshold. If this occurs the circuit will
become unstable.
Loss is implemented, in the chosen path, by
subtracting the value set by the Pad0 - Pad3 control
bits from the appropriate gain value set by the RxG0
- RxG3 or TxG0 - TxG3 control bits (see Digital Gain



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