MT9196AS datasheet(11/38 Pages) MITEL

11 / 38 page

Preliminary Information

MT9196

7-137

Figure 7 - ST-BUS Channel Assignment

F0i

DSTi,

DSTo

LSB first

for D-

Channel

MSB first for C, B1- & B2-

Channels

CHANNEL 0

D-channel

CHANNEL 1

C-channel

CHANNEL 2

B1-channel

CHANNEL 3

B2-channel

CHANNELS 4-31

Not Used

125

µs

between the IDPC and the microcontroller. At the

end of the two-byte transfer CS is brought high again

to terminate the session. The rising edge of CS will

tri-state the output driver of DATA1 which will remain

tri-stated as long as CS is high.

Intel processors utilize least significant bit first

transmission

while

Motorola/National

processors

employ most significant bit first transmission. The

IDPC microport automatically accommodates these

two schemes for normal data bytes. However, to

ensure timely decoding of the R/W and address

information, the Command/Address byte is defined

differently for Intel operation than it is for Motorola/

National operation. Refer to the relative timing

diagrams of Figures 5 and 6.

Receive data is sampled on the rising edge of SCLK

while transmit data is made available concurrent with

the falling edge of SCLK.

Detailed microport timing is shown in Figure 15.

Flexible Digital Interface

A serial link is required to transport data between the

IDPC and an external digital transmission device.

IDPC utilizes the ST-BUS architecture defined by

Mitel Semiconductor but also supports a strobed

data interface found on many standard CODEC

devices. This interface is commonly referred to as

Synchronous Serial Interface (SSI). The combination

of ST-BUS and SSI provides a Flexible Digital

Interface (FDI) capable of supporting all Mitel basic

rate transmission devices as well as many other

2B + D transceivers.

The required mode of operation is selected via the

ST-BUS/SSI

control

bit

(FDI

Control

address 10h). Pin definitions alter dependent upon

the operational mode selected, as described in the

following

subsections

well

the

Description tables.

Quiet Code

The FDI can be made to send quiet code to the

decoder and receive filter path by setting the

RxMUTE bit high. Likewise, the FDI will send quiet

code in the transmit (DSTo) path when the TxMUTE

bit is high. Both of these control bits reside in Control

are low their respective paths function normally. The

-Zero entry of Table 1 is used for the quiet code

definition.

ST-BUS Mode

The ST-BUS consists of output (DSTo) and input

(DSTi) serial data streams, in FDI these are named

Dout and Din respectively, a synchronous clock input

signal CLOCKin (C4i), and a framing pulse input

(F0i). These signals are direct connections to the

corresponding pins of Mitel basic rate devices. Note

that in ST-BUS mode the XSTL2 pin is not used. The

CSL1 and CSL0 bits, as described in the SSI Mode

section, are also ignored since the data rate is fixed

for ST-BUS operation. However, the Asynch/Synch

bit must be set to logic “0” for ST-BUS operation.

The data streams operate at 2048 kb/s and are Time

Division Multiplexed into 32 identical channels of 64

kb/s bandwidth. A frame pulse (a 244 nSec low going

pulse) is used to parse the continuous serial data

streams into the 32 channel TDM frames. Each

frame has a 125 µSecond period translating into an 8

kHz frame rate. A valid frame begins when F0i is

logic low coincident with a falling edge of C4i. Refer

to Figure 12 for detailed ST-BUS timing. C4i has a

frequency (4096 kHz) which is twice the data rate.

This clock is used to sample the data at the 3/4 bit-

cell position on DSTi and to make data available on

DSTo at the start of the bit-cell. C4i is also used to

clock the IDPC internal functions (i.e., Filter/CODEC,

Digital gain and tone generation) and to provide the

channel timing requirements.

The IDPC uses only the first four channels of the 32

channel frame. These channels are always defined,

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