Preliminary Information

MT9196

7-161

† Timing is over recommended temperature range & recommended power supply voltages.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

NOTE 1: Not production tested, guaranteed by design.

Figure 13 - SSI Synchronous Timing Diagram

Characteristics

Sym

Min

Max

Units

Test Conditions

1

BCL Clock Period

244

1953

ns

BCL=4096 kHz to 512 kHz

2

BCL Pulse Width High

122

ns

BCL=4096 kHz

3

BCL Pulse Width Low

122

ns

BCL=4096 kHz

4

BCL Rise/Fall Time

20

ns

Note 1

5

Strobe Pulse Width

ns

Note 1

6

Strobe setup time before BCL falling

80

ns

7

Strobe hold time after BCL falling

80

ns

8

Dout High Impedance to Active Low

from Strobe rising

90

ns

9

Dout High Impedance to Active High

from Strobe rising

90

ns

10 Dout Active Low to High Impedance

from Strobe falling

90

ns

11 Dout Active High to High Impedance

from Strobe falling

90

ns

12 Dout Delay (high and low) from BCL

rising

90

ns

13 Din Setup time before BCL falling

50

ns

14 Din Hold Time from BCL falling

50

ns

(BCL)

Din

Dout

STB

70%

30%

70%

30%

70%

30%

70%

30%

NOTE:

CLOCKin