MT9196

Preliminary Information

7-160

† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.

‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

* Note: TxINC and A/

µ and refer to Control Register 2, address 0Fh.

† Timing is over recommended temperature range & recommended power supply voltages.

‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

* Note: All conditions

→ data-data, data-HiZ, HiZ-data.

Figure 12 - ST-BUS Timing Diagram

Characteristics

Sym

Min

Max

Units

Test Conditions

1

Input voltage without overloading

CODEC

at MIC+

at AUXin

across M+/M-

1.63

0.580

1.63

0.580

2.90

1.03

Vp-p

Vp-p

Vp-p

Vp-p

Vp-p

Vp-p

TxINC = 0, A/

µ = 0*

TxINC = 1, A/

µ = 1*

TxINC = 1, A/

µ = 0*

TxINC = 1, A/

µ = 1*

TxINC = 0, A/

µ = 0*

TxINC = 1, A/

µ = 1*

Tx filter gain=0dB setting

2

Input impedance

50

10

k

Ω

k

Ω

M+/M-, MIC+

AUXin

Characteristics

Sym

Min

Max

Units

Test Conditions

1C4i Clock Period

244

ns

2C4i Clock High period

122

ns

3C4i Clock Low period

122

ns

4C4i Clock Transition Time

20

ns

5F0i Frame Pulse Setup Time

50

ns

6F0i Frame Pulse Hold Time

50

ns

7

DSTo Delay

100

125

ns

8

DSTi Setup Time

30

ns

9

DSTi Hold Time

30

ns

DSTo

DSTi

70%

30%

70%

30%

70%

30%

70%

30%

NOTE:

1 bit cell

C4i

F0i