DLPC910 datasheet(22/50 Pages) TI1

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DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

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7.3.7.5.2

VLED1

The VLED1 signal is typically connected to an LED indicator to show the status of system initialization and the

status of the clock circuits. The VLED1 signal is asserted only when system initialization is complete and clock

circuits are initialized. Logically, these signals are ANDed together to show an indication of the health of the

system. If the Phase Locked Loop (PLL) connected to the data clock and the DMD clock are functioning correctly

after system initialization, the LED will be illuminated.

7.3.8 Reset and System Clock

7.3.8.1 Controller Reset

The controller reset input CTRL_RSTZ is an active low, asynchronous reset. This reset can be sourced from a

voltage supervisor or from the customer interface. Users should note that the chipset will not operate correctly if

all DLPC910 power supplies are not in range at the time this reset is released.

7.3.8.2 Main Oscillator Clock

The reference clock, CLKIN_R, supplied from an oscillator must be 50MHz. This is required for the precise timing

used to perform the DMD MCP. This clock should be valid prior to releasing CTRL_RSTZ.

7.3.9 I2C Interface

The I2C interface is compliant to I2C specification version 1.0 – 1995, and operates between 100 kHz and 400

kHz clock rate. The interface allows the user to set controller configuration and provides status information such

as:

•

Controller and DMD identification

•

DMD Type

•

Versions

•

Controller operating status

•

Controller operating modes

Each I2C clock and data I/O requires an external 1K-

Ω pull-up resistor to 3.3 V. Depending on the speed that is

selected and the loading of the interface, a different pull-up resistor may be required.

7.3.9.1 Configuration Pins

The DDC_IIC_ADDR_SEL input signal allows the user to select the DLPC910 I2C slave address. When this pin

is low, the slave address is 0x34 and when high the slave address is 0x36. If pin is left unconnected, the default

slave address is 0x36.

The DDC_IIC_SCL is the master controller input clock. The DDC_IIC_SDA is the bidirectional data signal. Both

these signals require a 1-k

Ω pull-up resistor.

7.3.9.2 Communications Interface

Communications is performed over the I2C interface where the DLPC910 is the slave device. The DLPC910

slave address consists of a 7-bit address plus 1 R/W bit. Communicating with the DLPC910 involves writing to or

reading from the registers listed in Register Map.

7.3.9.2.1

Command Format

All register addresses are 32-bit in size, where each register contains a 32-bit value. The actual valid bits are

shown in each respective register. Most registers contain spare or unused bits. These bits should be treated as

don't-care during a read operation unless otherwise specified. When writing to spare or unused bits, these bits

MUST be set to 0. Both the register address and the data require the least-significant byte to be first and most-

significant byte last. A SUB CMD must precede the register address to indicate the type of operation, where a

0xF1 indicates a write operation and a 0xF2 indicates a read operation. The following figures show examples of

writing and reading to the DESTOP_BUS_SWAP register.

Figure 6 shows an I2C master writing data to the DLPC910, where 0xF1 is required as the SUB CMD followed

by the register address and finally the register data.

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