DLPC910 datasheet(24/50 Pages) TI1

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DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

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RESET_STRB – Reset Address, Mode, and Level Select latched on rising-edge.

7.3.10.5 Enable and Interrupt Signals

The controller provides the necessary outputs for DMD enables and an input interrupt from the DMD, which are:

•

PWRDNZ – Active-low DMD reset.

•

RESET_OEZ – Active-low output enable for the DMD reset driver circuits.

•

RESETZ – Active-low sets the reset circuits in known state.

•

RESET_IRQZ – Active-low input interrupt from the DMD.

7.3.10.6 Serial Control Port

The DLPC910 communicates with the DMD over the SCP bus to perform initialization, set configuration, and

retrieve identification information.

7.3.11 Flash PROM Interface

7.3.11.1 JTAG Interface

The JTAG interface has multiple purposes that can be used in the following manner:

•

Program the configuration bit stream directly into the DLPC910

•

Perform boundary test and debug of the DLPC910

•

Program the configuration bit stream directly into the DLPR910YVA PROM (not user configurable)

7.3.11.2 PGM Interface

The PGM(4:0) interface is used by the DLPC910 to read in the configuration bit stream from the attached

DLPR910YVA PROM.

7.4 Device Functional Modes

7.4.1 DMD Row Operation

The DMD data is loaded one row at a time with four LVDS buses into the DMD SRAM pixels. The DMD requires

all four data buses (A,B,C,D). Each bus consists of a differential clock (DDC_DCLKOUT), a differential control

signal (DDC_SCTRL), and 16 differential pairs of LVDS signals (DDC_DOUT[15:0]) that are output from the

DLPC910. Data and control are clocked into the DMD on both the rising and falling edges of the

DDC_DCLKOUT_[A, B, C, D]. Data loading does not cause mirror switching until a MCP operation is completed.

The number of clocks to load a row can be calculated as:

C = P / (D × E)

where

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C = number of clocks per row

•

P = number of pixels per row

•

D = data bus bit width

•

E = 2. (Data is clocked on both the rising an falling edge of DCLK.)

(1)

Example:

C = 2560 / (64 × 2) = 20 clocks per row

Row address orientation depends on the North or South Flip Flag (NS_FLIP) input to the DLPC910. Refer to

Related Documentation for the DMD datasheet regarding orientation of rows, columns, and MCP blocks. The row

address counter does not automatically wrap-around when using the increment row address pointer instruction.

After the final row is addressed, the row address pointer must be cleared to 0.

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