DLPC910 datasheet(23/50 Pages) TI1

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DLPC910 Slave Address

R/W

0xF2

0x28

0x00

0x01

0x00

A/A

0 (Write)

SUB CMD

DLPC910 Slave Address

R/W

1 (Read)

S DLPC910 Slave Address R/W

0xF1

0x28

0x00

0x01

0x00

A/A

0 (Write)

SUB CMD

From master to DLPC910

From DLPC910 to master

A = acknowledge (SDA Low)

A = not acknowledge (SDA High)

S = START Condition

P = STOP Condition

DLPC910

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DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

Figure 6. Example I2C Master Writing DLPC910 Register Data

Figure 7 shows an I2C master reading data from the DLPC910, where 0xF2 is required as the SUB CMD

followed by the register address. Then the master performs STOP followed by a START to read the register

data.

Figure 7. Example I2C Master Reading DLPC910 Register Data

7.3.10 DMD Interface

7.3.10.1 DDC_DOUT

The controller provides four (A, B, C, D) 16-bit wide 2x LVDS output data buses to the DMD with a user

selectable bus frequency of 400 or 480 Mhz.

7.3.10.2 DDC_SCTRL

The controller provides four (A, B, C, D) control output buses to the DMD. Each bus provides the necessary

control data for the different operating modes of the DMD.

7.3.10.3 DDC_DCLKOUT

The controller provides four (A, B, C, D) clock outputs to the DMD with a clock frequency of 400 or 480 Mhz

(user selectable). Both DDC_DOUT and DDC_SCTRL are clocked into the DMD on both the rising and falling

edges of the DDC_DCLKOUT.

7.3.10.4 DMD Reset Interface

7.3.10.4.1

Mirror Reset Control

The controller provides the necessary mirror reset control signals to the DMD, which are:

•

RESET_ADDR(3:0) – Reset Driver Address Select.

•

RESET_MODE(3:0) – Reset Driver Mode Select.

•

RESET_SEL(1:0) – Reset Driver Level Select.

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