DLPC910 datasheet(25/50 Pages) TI1

25 / 50 page

DCLKIN

DVALID

ROWMD/ROWAD

BLK_MD/BLK_AD

NS_FLIP/COMP_DATA

DIN_A/B/C/D

DLPC910

www.ti.com

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

Device Functional Modes (continued)

7.4.1.1 Data and Command Write Cycle

Once initialization is complete (INIT_ACTIVE = 0) the user is free to send data and control information to the

DLPC910. When the user asserts the DVALID signal for the LVDS input buses, the DLPC910 begins sampling

the LVDS data inputs and synchronously sending this information to the DMD along with row address control

information. The row cycle period is exactly 20 CLKS long and begins with DVALID. If DVALID is removed, the

DLPC910 stops loading data and control information until DVALID goes active again.

Figure 8 shows an example of data written to the DLPC910 for a single row. Data is written to the DMD 64 bits

(16 A bits + 16 B bits + 16 C bits + 16 D bits) on each clock edge. An entire line must be written for data to be

latched into memory.

The DMD incorporates single row write operations using a row address counter that is randomly addressable. As

shown in Table 1 and Table 2, ROWMD(1:0) determines the single row write count mode and ROWAD(10:0)

determines the single row write address. ROWMD and ROWAD must be asserted and de-asserted

synchronously with DVALID and must be valid synchronous to the beginning of the data as shown in Figure 8.

Figure 8. Single Row Write Operation

7.4.2 Block Mode Operation

The DMD mirrors and corresponding SRAM pixels are organized into blocks and each block is broken into rows

per BLK as described in Table 4. Mirror blocks are addressed for either the Mirror Clocking Pulse or Block Clear

functions by asserting block control signals at the start of each row data load. RST2BLKZ, BLK_MD and BLK_AD

are used as shown in Table 5 to designate which mirror block(s) is to be issued a MCP or a Block Clear. Refer to

Related Documentation for the DMD datasheet regarding block location information.

•

The clear operation sets all of the SRAM pixels in the designated block to logic zero during the current row

cycle.

•

It is possible to issue a MCP to a block while loading a different block.

•

It is not possible to clear a block while writing to a different block.

•

It is not necessary to clear a block if it is going to be reloaded with new data (just like a normal memory cell).

•

It is recommended that RST2BLKZ, COMP, and NS_FLIP be set to one value and not adjusted during normal

system operation.

•

A change in RST2BLKZ is not immediately effective and will require more than one row load cycle to

complete.

Submit Documentation Feedback

Product Folder Links: DLPC910

DLPC910 Datasheet(PDF) 25 Page - Texas Instruments

DLPC910 Datasheet(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL