DLPC910 datasheet(27/50 Pages) TI1

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DLPC910

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DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

Table 5. Block Operations (continued)

RST2BKLZ

BLK_MD 1

BLK_MD 2

BLK_AD 3

BLK_AD 2

BLK_AD 1

BLK_AD 0

OPERATION

Reset blocks 14-15

Reset blocks 00-03

Reset blocks 04-07

Reset blocks 08-11

Reset blocks 12-15

Reset blocks 00-15

Float blocks 00-15

7.4.3 Block Clear

The DMD incorporates block clear operations using the BLK_MD and BLK_AD signals as shown in Table 5. The

block address does not automatically increment and must be set to the desired block to be cleared. Block clear

operation writes logic zero data to all the SRAM cells in one DMD block regardless of the COMP_DATA input

state. It is not possible to clear a DMD block while writing to a different block. BLK_MD and BLK_AD are

asserted to perform a MCP on the block(s) that have been cleared. The customer interface should introduces a

delay on the last block(s) that were issued a MCP to allow the mirrors to become stable.Each Block Clear

operation must be followed by two no-op row load cycles. Therefore, 16 total Block Clear commands and 32

total no-op row cycles are required to clear the entire DMD array.

7.4.4 Mirror Clocking Pulse

A Mirror Clocking Pulse (MCP) sequence begins by asserting BLK_MD and BLK_AD for a single, dual, quad, or

global block operation as defined in Table 5. A MCP causes a reset on the block(s), and the data stored in the

block(s) takes effect on the mirrors of the DMD. Shortly after a MCP has been issued, RST_ACTIVE goes high

for approximately 4

μs, indicating a MCP operation is in progress. During this time, no additional MCPs may be

initiated until RST_ACTIVE returns low. RST_ACTIVE does not return to low unless continuous no-op or data

loading row cycles are issued. A typical single block load phased sequence in which consecutive DMD blocks

are loaded is illustrated in Figure 10. A MCP time is identical for single, dual, quad or global block operations.

Note that it may take longer to complete a MCP on a block than it does to load a block. The block load time may

be calculated as:

Block Load Time = Clock Period × number CLKS per ROW × number ROWS per BLK

Table 6. DMD Block Load Time at 480 MHz DMD Clock

DMD

MINIMUM BLOCK LOAD TIME

DLP9000XFLS

4.167 µsec

For any case which involves sending a MCP or a Block Clear without data loading, the customer interface must

send no-op row cycles. This can be accomplished by asserting DVALID, while holding ROWMD at 00 and

BLKMD at 00 for 20 clock cycles, as in Figure 9. Following the loading of all rows in a block or the entire DMD, at

least one no-op row cycle must be completed to initiate the MCP. If the MCP is asserted prior to loading all rows

in a block or the entire DMD, rows which were not updated will show old data. Additional MCP operations may

not be initiated until RST_ACTIVE is low. Block Clear operations for the DMD must be followed by two

consecutive no-op row cycle commands.

To obtain full utilization of the DMD bandwidth, load four blocks and then issue a MCP to the four blocks

concurrently by setting RST2BLKZ to 1 and BLK_MD to 11 with the appropriate address in BLK_AD. This is

illustrated in Figure 12.

It is possible to load other blocks while the block(s) previously issued a MCP is settling. This is illustrated in

Figure 11 and Figure 12, where blocks are reloaded while the mirror setting time is ocurring. It is also possible to

load other blocks while previously loaded block(s) have an outstanding RST_ACTIVE. This is illustrated in

Figure 12, where block 0 is loaded while RST_ACTIVE is asserted for blocks 12-15.

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