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DLPC910 Datasheet(PDF) 43 Page - Texas Instruments |
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DLPC910 Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 50 page ![]() DLPC910 www.ti.com DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015 • Vias should be spaced out to avoid forming slots on the power planes. • High speed signals should not cross over a slot in the adjacent power planes. • Placing extra vias is not required if there are sufficient ground vias due to normal ground connections of devices. 10.1.5 Power Vias Power and Ground pins of each component shall be connected to the power and ground planes with a via for each pin. Avoid sharing vias to the power plane among multiple power pins, where possible. Trace lengths for component power and ground pins should be minimized (ideally, less than 0.100 inch). Unused or spare device pins that are connected to power or ground may be connected together with a single via to power or ground. The minimum spacing between vias shall be 0.050 inch to prevent slots from being developed on the ground plane. 10.1.6 Decoupling Decoupling capacitors must be located as near as possible to the DLPC910 voltage supply pins. Capacitors should not share vias. The DLPC910 power pins can be connected directly to the decoupling capacitor (no via) if the trace is less than 0.03 inches. Otherwise the component should be tied to the voltage or ground plane through a separate via. All capacitors should be connected to the power planes with trace lengths less than 0.05 inches. 10.1.7 Flex Connector Plating For designs using the Texas Instruments designed reference flex cable, plate all the pad area on the top layer of flex connection with a minimum of 35 and maximum 50 micro-inches of electrolytic hard gold over a minimum of 100 micro-inches of electrolytic nickel. 10.2 Layout Example The PCB layer design may vary depending on system design. However, careful attention is required to meet design considerations. Table 25 shows a layer signal definition and Figure 17 shows a PCB stack-up. The PCB stack-up uses Hitachi 679gs as the dielectric material to improve the signal slew rate. Although the material shown is Rogers Theta, it is the same material as the Hitachi 679gs. Table 25. Layer Definition Top: Signal 2: GND 3: Signal 4: GND 5: Signal 6: GND 7: Signal 8: GND 9: Split Power 10: Split Power 11: GND 12: Signal 13: GND 14: Signal 15: GND 16: Signal 17: GND Bottom: Signal Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Links: DLPC910 |
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