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DLPC910 Datasheet(PDF) 10 Page - Texas Instruments |
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DLPC910 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 50 page ![]() DLPC910 DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015 www.ti.com Pin Functions (continued) PIN ACTIVE I/O TYPE CLOCK SYSTEM DESCRIPTION (HI OR LO) NAME NO. DDC_DOUT_D10_DPN L25 LVDS_25_NO - DDC_DCLKOUT_D Output Bus D Data bit 10 to DMD. DDC_DOUT_D10_DPP L24 LVDS_25_PO - DDC_DCLKOUT_D DDC_DOUT_D11_DPN K26 LVDS_25_NO - DDC_DCLKOUT_D Output Bus D Data bit 11 to DMD. DDC_DOUT_D11_DPP K25 LVDS_25_PO - DDC_DCLKOUT_D DDC_DOUT_D12_DPN J26 LVDS_25_NO - DDC_DCLKOUT_D Output Bus D Data bit 12 to DMD. DDC_DOUT_D12_DPP J25 LVDS_25_PO - DDC_DCLKOUT_D DDC_DOUT_D13_DPN J24 LVDS_25_NO - DDC_DCLKOUT_D Output Bus D Data bit 13 to DMD. DDC_DOUT_D13_DPP H24 LVDS_25_PO - DDC_DCLKOUT_D DDC_DOUT_D14_DPN H26 LVDS_25_NO - DDC_DCLKOUT_D Output Bus D Data bit 14 to DMD. DDC_DOUT_D14_DPP G26 LVDS_25_PO - DDC_DCLKOUT_D DDC_DOUT_D15_DPN G25 LVDS_25_NO - DDC_DCLKOUT_D Output Bus D Data bit 15 to DMD. DDC_DOUT_D15_DPP G24 LVDS_25_PO - DDC_DCLKOUT_D DDC_SCTRL_AN R1 LVDS_25_NO - DDC_DCLKOUT_A Output Bus A Serial Control to DMD. DDC_SCTRL_AP P1 LVDS_25_PO - DDC_DCLKOUT_A DDC_SCTRL_BN AA3 LVDS_25_NO - DDC_DCLKOUT_B Output Bus B Serial Control to DMD. DDC_SCTRL_BP AB4 LVDS_25_PO - DDC_DCLKOUT_B DDC_SCTRL_CN W20 LVDS_25_NO - DDC_DCLKOUT_C Output Bus C Serial Control to DMD. DDC_SCTRL_CP W21 LVDS_25_PO - DDC_DCLKOUT_C DDC_SCTRL_DN N26 LVDS_25_NO - DDC_DCLKOUT_D Output Bus D Serial Control to DMD. DDC_SCTRL_DP P26 LVDS_25_PO - DDC_DCLKOUT_D DVALID_A_DPN D20 LVDS_25_NI - DDC_DCLK_A Input Bus A Data Valid Signal. 100- Ω internal LVDS termination. DVALID_A_DPP D21 LVDS_25_PI - DDC_DCLK_A DVALID_B_DPN C8 LVDS_25_NI - DDC_DCLK_B Input Bus B Data Valid Signal. 100- Ω internal LVDS termination. DVALID_B_DPP D8 LVDS_25_PI - DDC_DCLK_B DVALID_C_DPN L19 LVDS_25_NI - DDC_DCLK_C Input Bus C Data Valid Signal. 100- Ω internal LVDS termination. DVALID_C_DPP L20 LVDS_25_PI - DDC_DCLK_C DVALID_D_DPN L3 LVDS_25_NI - DDC_DCLK_D Input Bus D Data Valid Signal. 100- Ω internal LVDS termination. DVALID_D_DPP L4 LVDS_25_PI - DDC_DCLK_D DDC_VERSION_0 F18 LVCMOS25_O Hi - DLPC910 Firmware Rev Number bit 0 DDC_VERSION_1 G17 LVCMOS25_O Hi - DLPC910 Firmware Rev Number bit 1 DDC_VERSION_2 H18 LVCMOS25_O Hi - DLPC910 Firmware Rev Number bit 2 SPEED_SEL_0 H8 LVCMOS25_I Hi - Speed_Sel[1:0] = 00 400Mhz = 01 480Mhz SPEED_SEL_1 H9 LVCMOS25_I Hi - = 10, 11 Reserved Includes internal pull- ups. Reserved. Do not connect. Includes VSP_ENABLE E8 LVCMOS25_I Hi - internal pull-up. DLPR910 Initialization complete. ECP2_FINISHED E25 LVCMOS25_O Hi - Connected to LED. VLED0 AA17 LVCMOS25_O Hi = On - Power Indicator LED Output. VLED1 AB17 LVCMOS25_O Hi = On - Heartbeat Indicator LED Output. DMD Reset Pulse Watchdog Timer WDT_ENBLZ F25 LVCMOS25_I Lo - Enable PWR_FLOAT G9 LVCMOS25_I Hi - Park DMD mirrors. NS_FLIP F19 LVCMOS25_I Hi - Top/Bottom image flip on DMD COMP_DATA G19 LVCMOS25_I Hi DDC_DCLK_[A,B,C,D] Compliment Data (0 <--> 1) INIT_ACTIVE E26 LVCMOS25_O Hi - DLPC910 Initialization Routine Active RST_ACTIVE G10 LVCMOS25_O Hi - DMD Mirror Clocking Pulse in progress RST2BLKZ E18 LVCMOS25_I Hi - Dual and Quad Block control No connect. For access to test point TST_PT_0 Y12 LVCMOS33_O - - output route to test via. No connect. For access to test point TST_PT_1 AA12 LVCMOS33_O - - output route to test via. No connect. For access to test point TST_PT_2 Y13 LVCMOS33_O - - output route to test via. No connect. For access to test point TST_PT_3 AA13 LVCMOS33_O - - output route to test via. 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DLPC910 |
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