DLPC910 datasheet(34/50 Pages) TI1

34 / 50 page

DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

www.ti.com

7.5.1.7 DESTOP_RESET_REG Register

The DESTOP_RESET_REG register is used for reading the current state of the MCP. Reading this register while

the DLPC910 is loading data to the DMD may always indicate a “1”. It is best to monitor the actual RST_ACTIVE

output signal of the DLPC910 to obtain the real state of the MCP.

Table 14. DESTOP_RESET_REG Register

ADDRESS

BITS

DESCRIPTION

RESET

TYPE

0x0020

RESET Operation in progress bit: (Mirror clocking pulse)

0x0

0 - Reset inactive

1 - Reset active

31:1

UNUSED

0x0

7.5.1.8 DESTOP_INFIFO_STATUS Register

The DESTOP_INFIFO_STATUS register is used for validating there is data in the input bus FIFO buffers. An

empty FIFO buffer may indicate that the DVALID is not properly set for the data on the input data bus.

Table 15. DESTOP_INFIFO_STATUS Register

ADDRESS

BITS

DESCRIPTION

RESET

TYPE

0x0024

Channel A input FIFO status:

0x0

0 - Channel A FIFO has data

1 - Channel A FIFO is empty

Channel B input FIFO status:

0x0

0 - Channel B FIFO has data

1 - Channel B FIFO is empty

Channel C input FIFO status:

0x0

0 - Channel C FIFO has data

1 - Channel C FIFO is empty

Channel D input FIFO status:

0x0

0 - Channel D FIFO has data

1 - Channel D FIFO Is empty

31:4

UNUSED

0x0

7.5.1.9 DESTOP_BUS_SWAP Register

The DESTOP_BUS_SWAP register is used for configuring the DLPC910 output LVDS buses to the DMD. To

simplify board layout design, swapping the buses may reduce routing constraints. If the buses are swapped in

hardware, then the appropriate setting that matches the hardware must be set after a power cycle or a reset to

the DLPC910.

Table 16. DESTOP_BUS_SWAP Register

ADDRESS

BITS

DESCRIPTION

RESET

TYPE

0x0028

Enables Bus swap for A and B output DMD buses. SCTRLs

0x0

R/W

for A and B output buses are also swapped.

0 = un-swapped (default)

1 = swapped

Enables Bus swap for C and D output DMD buses.

0x0

R/W

SCTRLs for C and D output buses are also swapped.

0 = un-swapped (default)

1 = swapped

31:2

UNUSED

0x0

Submit Documentation Feedback

Product Folder Links: DLPC910

DLPC910 Datasheet(PDF) 34 Page - Texas Instruments

DLPC910 Datasheet(HTML) 34 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL