DLPC910 datasheet(30/50 Pages) TI1

30 / 50 page

DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

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7.4.5 DMD Array Subset

It is possible to use a subset of the DMD array including individual MCP blocks. The driving software/hardware

MUST ensure that the MCP rate for the number of blocks in the subset plus the mirror settling time does not

exceed 50 kHz.

Load4 functionality is primarily intended to be used with global MCPs. However, it is possible to use a subset of

the DMD array including individual MCP blocks. The driving software/hardware MUST ensure that the MCP rate

for the number of blocks in the Load4 subset plus the mirror settling time does not exceed 50 kHz.

7.4.6 Global Mirror Clocking Pulse Consideration

A Global MCP (BLK_MD = 11 and BLK_AD = 10XX), takes the same amount of time as the single, dual, and

quad block MCP. In addition to requiring a no-op row cycle to initiate a global MCP, a row cycle (either no-op or

data loading) is also required to complete the operation. If the customer interface is monitoring RST_ACTIVE to

determine when to send a subsequent row cycle, it will never see RST_ACTIVE transition low. One method of

operation would be to continue sending no-op row cycles until RST_ACTIVE goes low then continue loading data

with real row cycles. Another method of operation is to delay greater than 10

μs, then start loading new data to

DMD.

7.5 Register Map

7.5.1 Register Table Overview

Table 7 lists the I2C accessible memory mapped registers for the DLPC910. Access to the I2C registers should

not begin unitl INIT_ACTIVE has transitioned low (logic 0).

Table 7. Communication Registers

ADDRESS

DESCRIPTION

SIZE

0x0000

DESTOP_INTERRUPT

DESTOP Interrupt Status

0x0004

0x0008

0x000C

MAIN_STATUS

Main Status

0x0010

DESTOP_CAL

DESTOP input calibration status

0x0014

DESTOP_DMD_ID_REG

Connected DMD ID

0x0018

DESTOP_CATBITS_REG

Connected DMD fuse catalog bits

0x001C

DESTOP_910VERSION_REG

DLPC910 Version Number

0x0020

DESTOP_RESET_REG

Reset status signals

0x0024

DESTOP_INFIFO_STATUS

Input interface FIFO status

0x0028

DESTOP_BUS_SWAP

Output bus swap

0x002C

DESTOP_DMDCTRL

DMD Control Register

0x0030

DESTOP_BIT_FLIP

Output data bus bit reversal/flip

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