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3.12.8

DMA Transfer in Doubleword Mode

3.12.9

DMA Channel Index Registers

3.12.10

DMA Interrupts

3.12.11

DMA Controller Synchronization Events

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two

consecutive 16-bit transfers are initiated and the source and destination addresses are automatically

updated following each transfer. In this mode, each 32-bit word is considered to be one element.

The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA

transfer mode control register (DMMCRn). Unlike basic address adjustment, in conjunction with the frame

index DMFRI0 and DMFRI1, the DMA allows different adjustment amounts depending on whether or not

the element transfer is the last in the current frame. The normal adjustment value (element index) is

contained in the element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for

the end of the frame, is determined by the selected DMA frame index register, either DMFRI0 or DMFRI1.

The element index and the frame index affect address adjustment as follows:

• Element index: For all except the last transfer in the frame, the element index determines the amount

to be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as

selected by the SIND/DIND bits.

• Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as

selected by the SIND/DIND bits. This occurs in both single-frame and multiframe transfers.

The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is

determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The

available modes are shown in Table 3-11.

Table 3-11. DMA Interrupts

MODE

DINM

IMOD

INTERRUPT

ABU (non-decrement)

At full buffer only

ABU (non-decrement)

At half buffer and full buffer

Multiframe

At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)

Multiframe

At end of frame and end of block (DMCTRn = 0)

Either

No interrupt generated

Either

No interrupt generated

The transfers associated with each DMA channel can be synchronized to one of several events. The

DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of

possible events and the DSYN values are shown in Table 3-12.

Table 3-12. DMA Synchronization Events

DSYN VALUE

DMA SYNCHRONIZATION EVENT

0000b

No synchronization used

0001b

McBSP0 receive event

0010b

McBSP0 transmit event

0011b

McBSP2 receive event

0100b

McBSP2 transmit event

Functional Overview

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