TMS320VC5416 datasheet(15/98 Pages) TI

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TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

Table 2-2. Signal Descriptions (continued)

TERMINAL

I/O(1)

DESCRIPTION

NAME

HOST-PORT INTERFACE SIGNALS

Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the

HPI registers. These pins can also be used as general-purpose I/O pins. HD0-HD7 is placed in the

HD0-

high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to

I/O/Z

HD7(2)(3)

reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven

by the device, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled

at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs.

HCNTL0(4)

Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs

HCNTL1(4)

have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16 = 1.

Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup

HBIL(4)

resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1.

Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input

HCS (2) (4)

has an internal pullup resistor that is only enabled when HPIENA = 0.

HDS1 (2) (4)

Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe

HDS2 (2) (4)

inputs have internal pullup resistors that are only enabled when HPIENA = 0.

Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA

HAS (2) (4)

Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is only

HR/W(4)

enabled when HPIENA = 0.

Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host

HRDY

O/Z

when the HPI is ready for the next transfer. This pin is driven high during reset.

Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT

HINT

O/Z

goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1.

HPI module select. HPIENA must be tied to DVDD to have HPI selected. If HPIENA is left open or connected to

ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus

HPIENA(5)

has holders set. HPIENA is provided with an internal pulldown resistor that is always active. HPIENA is sampled

when RS goes high and is ignored until RS goes low again. This pin should never be changed while reset is

high.

HPI16 mode selection. This pin must be tied to DVDD to enable HPI16 mode. The pin has an internal pulldown

HPI16(5)

resistor which is always active. If HPI16 is left open or driven low, the HPI16 mode is disabled.

SUPPLY PINS

CVSS

Ground. Dedicated ground for the core CPU

CVDD

+VDD. Dedicated power supply for the core CPU

DVSS

Ground. Dedicated ground for I/O pins

DVDD

+VDD. Dedicated power supply for I/O pins

TEST PINS

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The

changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction

TCK(2)(4)

on the falling edge of TCK.

IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register

TDI(4)

(instruction or data) on a rising edge of TCK.

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out

TDO

O/Z

of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in

progress. TDO also goes into the high-impedance state when OFF is low.

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into

TMS(4)

the TAP controller on the rising edge of TCK.

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the

TRST (5)

operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and

the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST

EMU0(6)

I/O/Z

is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by

way of the IEEE standard 1149.1 scan system.

(4)

This pin has an internal pullup resistor.

(5)

This pin has an internal pulldown resistor.

(6)

This pin must be pulled up with a 4.7-k

Ω resistor to ensure the device is operable in functional mode or emulation mode.

Introduction

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