TMS320VC5416 datasheet(45/98 Pages) TI

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3.15

Memory-Mapped Registers

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

Table 3-14. Device ID Register (CSIDR) Bits

BIT

FUNCTION

15-8

Chip ID (hex code of 16)

7-4

Chip revision ID

3-0

Subsystem ID (0000b for single core devices)

The device has 27 memory-mapped CPU registers, which are mapped in data memory space address 0h

to 1Fh. Each device also has a set of memory-mapped registers associated with peripherals. Table 3-15

gives a list of CPU memory-mapped registers (MMRs) available. Table 3-16 shows additional peripheral

MMRs associated with the device.

Table 3-15. CPU Memory-Mapped Registers

ADDRESS

NAME

DESCRIPTION

DEC

HEX

IMR

Interrupt mask register

IFR

Interrupt flag register

—

2-5

Reserved for testing

ST0

Status register 0

ST1

Status register 1

Accumulator A low word (15-0)

Accumulator A high word (31-16)

Accumulator A guard bits (39-32)

Accumulator B low word (15-0)

Accumulator B high word (31-16)

Accumulator B guard bits (39-32)

TREG

Temporary register

TRN

Transition register

AR0

Auxiliary register 0

AR1

Auxiliary register 1

AR2

Auxiliary register 2

AR3

Auxiliary register 3

AR4

Auxiliary register 4

AR5

Auxiliary register 5

AR6

Auxiliary register 6

AR7

Auxiliary register 7

Stack pointer register

Circular buffer size register

BRC

Block repeat counter

RSA

Block repeat start address

REA

Block repeat end address

PMST

Processor mode status (PMST) register

XPC

Extended program page register

—

Reserved

Functional Overview

TMS320VC5416 Datasheet(PDF) 45 Page - Texas Instruments

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