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TMS320VC5416 Datasheet(PDF) 79 Page - Texas Instruments

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Part # TMS320VC5416
Description  TMS320VC5416 Fixed-Point Digital Signal Processor
PDF  98 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320VC5416 Datasheet(HTML) 79 Page - Texas Instruments

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Bit(n-1)
(n-2)
(n-3)
BCLKR
BFSR (int)
BFSR (ext)
BDR
tw(BCKRXH)
tc(BCKRX)
tw(BCKRXL)
td(BCKRH-BFRV)
td(BCKRH-BFRV)
tsu(BFRH-BCKRL)
th(BCKRL-BFRH)
th(BCKRL-BDRV)
tsu(BDRV-BCKRL)
tr(BCKRX)
tf(BCKRX)
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O – MARCH 1999 – REVISED JANUARY 2005
Table 5-21. McBSP Transmit and Receive Switching Characteristics
(1)
5416-120
5416-160
PARAMETER
UNIT
MIN
MAX
tc(BCKRX)
Cycle time, BCLKR/X(2)
BCLKR/X int
4P(3)
ns
tw(BCKRXH)
Pulse duration, BCLKR/X high(2)
BCLKR/X int
D – 1(4)
D + 1(4)
ns
tw(BCKRXL)
Pulse duration, BCLKR/X low(2)
BCLKR/X int
C – 1(4)
C + 1(4)
ns
BCLKR int
– 3
3
ns
td(BCKRH-BFRV)
Delay time, BCLKR high to internal BFSR valid
BCLKR ext
0
6
ns
BCLKX int
– 1
5
td(BCKXH-BFXV)
Delay time, BCLKX high to internal BFSX valid
ns
BCLKX ext
3
11
BCLKX int
6
Disable time, BCLKX high to BDX high impedance following last data
tdis(BCKXH-BDXHZ)
ns
bit of transfer
BCLKX ext
10
BCLKX int
– 1(5)
10
DXENA = 0
BCLKX ext
3
20
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
ns
BCLKX int
– 1(5)
20
DXENA = 1
BCLKX ext
3
30
BFSX int
–1(5)
7
Delay time, BFSX high to BDX valid
td(BFXH-BDXV)
ns
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
BFSX ext
3
11
(1)
CLKRP = CLKXP = FSRP = FSXP = 0. If the polaritiy of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2)
Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be
achievable at maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A
separate detailed timing analysis should be performend for each specific McBSP interface.
(3)
P = 0.5 * processor clock.
(4)
T = BCLKRX period = (1 + CLKGDV) * 2P
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 +1) * 2P when CLKGDV is even
(5)
Minimum delay times also represent minimum output hold times.
Figure 5-21. McBSP Receive Timings
Electrical Specifications
79



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