TMS320VC5416 datasheet(14/98 Pages) TI

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TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

Table 2-2. Signal Descriptions (continued)

TERMINAL

I/O(1)

DESCRIPTION

NAME

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the

device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the

READY

processor performs ready detection if at least two software wait states are programmed. The READY signal is

not sampled until the completion of the software wait states.

Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally

R/W

O/Z

in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the

high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.

I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O

IOSTRB

O/Z

device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance

state when OFF is low.

Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by

HOLD

the device, these lines go into the high-impedance state.

Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the

address, data, and control lines are in the high-impedance state, allowing them to be available to the external

HOLDA

O/Z

circuitry. HOLDA also goes into the high-impedance state when OFF is low. Figure 2-2 This pin is driven high

during reset.

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait

states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive

MSC

O/Z

high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external

wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF

is low.

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address

IAQ

O/Z

bus and goes into the high-impedance state when OFF is low.

TIMER SIGNALS

Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as

CLKOUT

O/Z

configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the ma-

chine-cycle rate divided by 4.

Clock mode select signals. CLKMD1-CLKMD3 allow the selection and configuration of different clock modes

CLKMD1(2)

such as crystal, external clock, and PLL mode. The external CLKMD1-CLKMD3 pins are sampled to determine

CLKMD2(2)

the desired clock generation mode while RS is low. Following reset, the clock generation mode can be

CLKMD3(2)

reconfigured by writing to the internal clock mode register in software.

Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is

X2/CLKIN(2)

revision-dependent, see Section Section 3.10 for additional information.)

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left

unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision-dependent, see

Section Section 3.10 for additional information.)

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT

TOUT

O/Z

cycle wide. TOUT also goes into the high-impedance state when OFF is low.

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),AND

MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS

BCLKR0(2)

Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following

BCLKR1(2)

I/O/Z

reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BCLKR2(2)

BDR0, BDR1,

Serial data receive input

BDR2

BFSR0,

Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured

BFSR1,

I/O/Z

as an input following reset. The BFSR pulse initiates the receive data process over BDR.

BFSR2

BCLKX0(2)

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as

BCLKX1(2)

I/O/Z

an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state

BCLKX2(2)

when OFF goes low.

BDX0, BDX1,

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is

O/Z

BDX2

asserted, or when OFF is low.

BFSX0,

Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over

BFSX1,

I/O/Z

BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX

BFSX2

goes into the high-impedance state when OFF is low.

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