TMS320VC5416 datasheet(91/98 Pages) TI

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tc(DSH−DSH)

tw(DSH)

tsu(HBV−DSL)

tw(DSL)

th(DSL−HBV)

tsu(HAV−DSL)

th(DSH−HDV)R

tv(HYH−HDV)

td(DSL−HYL)

HCS

HDS

HR/W

HA[17:0]

HD[15:0]

HRDY

Valid Address

Data

Valid Address

tsu(HBV−DSL)

th(DSL−HBV)

td(DSL−HDV1)

Data

td(DSL−HDV1)

tv(HYH−HDV)

th(DSH−HDV)R

td(DSL−HYL)

th(DSH−HAV)

td(DSL−HDD)

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

Table 5-35. HPI16 Mode Switching Characteristics

5416-120

5416-160

PARAMETER

UNIT

MIN

MAX

td(DSL-HDD)

Delay time, DS low to HD driven

Case 1a: Memory accesses initiated immediately following a write

48P + 20 – tw(DSH)

when DMAC is active in 32-bit mode and tw(DSH) was < 26P

Case 1b: Memory access not immediately following a write when

24P + 20

DMAC is active in 32-bit mode

Case 1c: Memory accesses initiated immediately following a write

Delay time, DS

32P + 20 – tw(DSH)

when DMAC is active in 16-bit mode and tw(DSH) was < 18P

low to HD valid

td(DSL-HDV1)

for first word of Case 1d: Memory accesses not immediately following a write when

16P + 20

an HPI read

DMAC is active in 16-bit mode

Case 2a: Memory accesses initiated immediately following a write

20P + 20 – tw(DSH)

when DMAC is inactive and tw(DSH) was < 10P

Case 2b: Memory accesses not immediately following a write when

10P + 20

DMAC is inactive

Memory writes when no DMA is active

10P + 5

Delay time, DS

td(DSH-HYH)

high to HRDY

Memory writes with one or more 16-bit DMA channels active

16P + 5

high

Memory writes with one or more 32-bit DMA channels active

24P + 5

tv(HYH-HDV)

Valid time, HD valid after HRDY high

th(DSH-HDV)R

Hold time, HD valid after DS rising edge, read

td(COH-HYH)

Delay time, CLKOUT rising edge to HRDY high

td(DSL-HYL)

Delay time, DS low to HRDY low

td(DSH-HYL)

Delay time, DS high to HRDY low

Figure 5-32. Nonmultiplexed Read Timings

Electrical Specifications

TMS320VC5416 Datasheet(PDF) 91 Page - Texas Instruments

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