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TMS320VC5416 Datasheet(PDF) 67 Page - Texas Instruments

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Part # TMS320VC5416
Description  TMS320VC5416 Fixed-Point Digital Signal Processor
PDF  98 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320VC5416 Datasheet(HTML) 67 Page - Texas Instruments

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5.5.5
Ready Timing for Externally Generated Wait States
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O – MARCH 1999 – REVISED JANUARY 2005
Table 5-13 and Table 5-14 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-10, Figure 5-11, Figure 5-12, and Figure 5-13).
Table 5-13. Ready Timing Requirements for Externally Generated Wait States
(1)
5416-120
5416-160
UNIT
MIN
MAX
tsu(RDY)
Setup time, READY before CLKOUT low
7
ns
th(RDY)
Hold time, READY after CLKOUT low
0
ns
tv(RDY)MSTRB
Valid time, READY after MSTRB low(2)
4H – 4
ns
th(RDY)MSTRB
Hold time, READY after MSTRB low(2)
4H
ns
tv(RDY)IOSTRB
Valid time, READY after IOSTRB low(2)
4H – 4
ns
th(RDY)IOSTRB
Hold time, READY after IOSTRB low(2)
4H
ns
(1)
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states
by READY, as least two software wait states must be programmed. READY is not sampled until the completion of the internal software
wait states.
(2)
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Table 5-14. Ready Switching Characteristics for Externally Generated Wait States
(1)
5416-120
5416-160
PARAMETER
UNIT
MIN
MAX
td(MSCL)
Delay time, CLKOUT low to MSC low
0
4
ns
td(MSCH)
Delay time, CLKOUT low to MSC high
0
4
ns
(1)
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states
by READY, as least two software wait states must be programmed. READY is not sampled until the completion of the internal software
wait states.
67
Electrical Specifications



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