TMS320VC5416 datasheet(19/98 Pages) TI

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3.3

On-Chip RAM

3.4

On-Chip Memory Security

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

The standard on-chip ROM layout is shown in Table 3-1.

Table 3-1. Standard On-Chip ROM Layout

ADDRESS RANGE

DESCRIPTION

C000h-D4FFh

ROM tables for the GSM EFR speech codec

D500h-F7FFh

Reserved

F800h-FBFFh

Bootloader

FC00h-FCFFh

µ-Law expansion table

FD00h-FDFFh

A-Law expansion table

FE00h-FEFFh

Sine look-up table

FF00h-FF7Fh

Reserved(1)

FF80h-FFFFh

Interrupt vector table

(1)

In the ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must

reserve these 128 words at addresses FF00h-FF7Fh in program space.

The device contains 64K-word

× 16-bit of on-chip dual-access RAM (DARAM) and 64K-word × 16-bit of

on-chip single-access RAM (SARAM).

The DARAM is composed of eight blocks of 8K words each. Each block in the DARAM can support two

reads in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address

range 0080h-7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit

to one. The other four blocks of DARAM are located in the address range 18000h-1FFFFh in program

space. The DARAM located in the address range 18000h-1FFFFh in program space can be mapped into

data space by setting the DROM bit to one.

The SARAM is composed of eight blocks of 8K words each. Each of these eight blocks is a single-access

memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a

data word is written to another SARAM block. The SARAM is located in the address range

28000h-2FFFFh, and 38000h-3FFFFh in program space.

The device has a maskable option to protect the contents of on-chip memories.

When the RAM/ROM security option is selected, the following restrictions apply:

• Only the on-chip ROM originating instructions can read the contents of the on-chip ROM; on-chip RAM

and external RAM originating instruction can not read data from ROM: instead 0FFFFh is read. Code

can still branch to ROM from on-chip RAM or external program memory.

• The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external

memory. To protect the internal RAM, the user must never branch to external memory.

• The security feature completely disables the scan-based emulation capability of the 54x to prevent the

use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG

boundary scan test capability.

• The device is internally forced into microcomputer mode at reset (MP/MC bit forced to zero),

preventing the ROM from being disabled by the external MP/MC pin. The status of the MP/MC bit in

the PMST register can be changed after reset by the user application.

• HPI writes have no restriction, but HPI reads are restricted to the 4000h - 5FFFh address range.

Functional Overview

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