DP83820 datasheet(33/87 Pages) NSC

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4.0 Register Set (Continued)

4.1.2 Configuration Command and Status Register

The CFGCS register has two parts. The upper 16-bits (31-16) are devoted to device status. The lower 16-bits (15-0) are

devoted to command and are used to configure and control the device.

Tag: CFGCS

Size: 32 bits

Hard Reset: 02900000h

Offset: 04h

Access: Read Write

Soft Reset: Unchanged

bit

tag

description

usage

31-16

STS

Status

Device Status Bits. A status bit is reset whenever the register is written, and

the corresponding bit location is a 1.

DPERR

Detected Parity Error

Refer to the description in the PCI V2.2 specification.

SSERR

Signaled SERR

Refer to the description in the PCI V2.2 specification.

RMABT

Received Master Abort

Refer to the description in the PCI V2.2 specification.

RTABT

Received Target Abort

Refer to the description in the PCI V2.2 specification.

STABT

Sent Target Abort

Refer to the description in the PCI V2.2 specification.

26-25

DSTIM

DEVSELN Timing

This field will always be set to 01 indicating that DP83820 supports

“medium” DEVSELN timing.

DPD

Data Parity Detected

Refer to the description in the PCI V2.2 specification.

FBB

Fast Back-to-Back Capable

DP83820 will set this bit to 1.

unused (reads return 0)

M66_CAP

66MHz Capable

This field indicates the device is 66MHz capable. It will be loaded from

EEPROM.

NCPEN

New Capabilities Enable

When set, this bit indicates that the Capabilities Pointer contains a valid

value and new capabilities such as power management are supported.

When clear, new capabilities (CAPPTR, PMCAP, PMCS) are disabled. The

value in this register will either be loaded from the EEPROM or, if the

EEPROM is disabled, from a strap option at reset.

19-16

Unused

Unused (reads return 0)

15-0

CMD

Command

Device Command bits (see below).

15-10

Unused

Unused (reads return 0)

FBBEN

Fast Back-to-Back Enable

Set to 1 by the PCI BIOS to enable the DP83820 to do Fast Back-to-Back

transfers (FBB transfers as a master is not implemented in the current

revision).

SERREN

SERRN Enable

When set, DP83820 will generate SERRN when an address parity error is

detected.

Unused

Unused (reads return 0)

PERRSP

Parity Error Response

When set, DP83820 will assert PERRN on the detection of a data parity

error when acting as the target, and will sample PERRN when acting as the

initiator. When reset, data parity errors are ignored. The action taken is

specified by CFG: PESEL.

Unused

Unused (reads return 0)

MWIEN

Memory Write and Invalidate

Enable

When set, DP83820 may use the Memory Write and Invalidate command

for qualifying transfers. If 0, Memory Write will always be used instead of

MWI. The DP83820 further qualifies enabling the MWI command using the

MWI_DIS bit in the CFG operational register.

Unused

Unused (reads return 0)

BMEN

Bus Master Enable

When set, DP83820 is allowed to act as a PCI bus master. When reset,

DP83820 is prohibited from acting as a PCI bus master.

MSEN

Memory Space Access

When set, DP83820 responds to memory space accesses. When reset,

DP83820 ignores memory space accesses.

IOSEN

IO Space Access

When set, DP83820 responds to IO space accesses. When reset,

DP83820 ignores IO space accesses.

DP83820 Datasheet(PDF) 33 Page - National Semiconductor (TI)

DP83820 Datasheet(HTML) 33 Page - National Semiconductor (TI)

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