DP83820 datasheet(53/87 Pages) NSC

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4.0 Register Set (Continued)

4.2.17 Priority Queueing Control Register

This register allows control of Priority Queueing features.

5-1

DRTH

Rx Drain Threshold

Specifies the drain threshold in units of 8 bytes. When the number of bytes

in the receive FIFO reaches this value (times 8), or the FIFO contains a

complete packet, the receive bus master state machine will begin the

transfer of data from the FIFO to host memory. Care must be taken when

setting DRTH to a value lower than the number of bytes needed to

determine if packet should be accepted or rejected. In this case, the packet

might be rejected after the bus master operation to begin transferring the

packet into memory has begun. When this occurs, neither the OK bit or any

error status bit in the descriptor’s cmdsts will be set. A value of 0 prevents

draining of the packet until it is completely received.

This value is also used to compare with the accumulated packet length for

early receive indication. When the accumulated packet length meets or

exceeds the DRTH value, the RXEARLY interrupt condition is generated. A

value of 0 prevents the RXEARLY interrupt.

unused.

Tag: PQCR

Size: 32 bits

Hard Reset: 00000000h

Offset: 003Ch

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

31-4

unused

3-2

RXPQ

Receive Priority

Queue Enable

This 2-bit field is used to enable Receive Priority Queueing. The number of priority

queues is determined by the following encoding:

00 - Disabled (one queue)

01 - Two queues (0,1)

10 - Three queues (0,1,2)

11 - Four queues (0,1,2,3)

Packets are queued to the priority queues based on the VLAN user_priority field in the

VLAN tag. Any packet without a VLAN tag will be assumed to be priority 0.

TXFAIR

Transmit Fairness

Enable

Enables fairness in the transmit priority queueing process. If set, the transmitter will

implement a rotating priority scheme so all queues get fair access. The highest priority for

the current descriptor selection is always one less than the previous priority. If the last

packet was priority 2, then the priority scheme is 1,0,3,2 from highest to lowest. If no

descriptors are available, the fairness algorithm will be reset such that priority 3 is highest

priority. If this bit is not set, then priority queue 3 will always have the highest priority.

TXPQEN

Transmit Priority

Queueing Enable

Enables the transmit priority queueing feature. If this bit is set, the transmit DMA engine

will select between the available priority queues for transmit data. The priority queues can

be enabled individually using the Command Register (CR) TXE and TXPRI bits. If this bit

is not set, then only the lowest priority queue (TXDP) is enabled, and the TXPRI bits have

no function.

DP83820 Datasheet(PDF) 53 Page - National Semiconductor (TI)

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