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4.0 Register Set (Continued)

4.2.14 Receive Descriptor Pointer Register

This register points to the current Receive Descriptor.

4.2.15 Receive Descriptor Pointer High Dword Register

This register points to the upper 32-bits of the current Receive Descriptor for 64-bit addressing. If Receive Priority

Queueing is enabled, this becomes the Descriptor pointer for all priority queues.

GP1_OE

General Purpose Pin 1

Output Enable

Enables the GP1 pin for use as an output. This bit is loaded from EEPROM

at power-up. R/W

GP5_OUT

General Purpose Pin 5

Output Value

Controls the output value on the GP5_DUP pin if the GP5_OE bit is set.

This bit is loaded from EEPROM at power-up. R/W

GP4_OUT

General Purpose Pin 4

Output Value

Controls the output value on the GP4 pin if the GP4_OE bit is set. This bit is

loaded from EEPROM at power-up.

GP3_OUT

General Purpose Pin 3

Output Value

Controls the output value on the GP3 pin if the GP3_OE bit is set. This bit is

loaded from EEPROM at power-up. R/W

GP2_OUT

General Purpose Pin 2

Output Value

Controls the output value on the GP2 pin if the GP2_OE bit is set. This bit is

loaded from EEPROM at power-up.

GP1_OUT

General Purpose Pin 1

Controls the output value on the GP1 pin if the GP1_OE bit is set. This bit is

loaded from EEPROM at power-up. R/W

Tag: RXDP

Size: 32 bits

Hard Reset: 00000000h

Offset: 0030h

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

31-3

RXDP

Receive Descriptor Pointer

The current value of the receive descriptor pointer. When the receive state

machine is idle, software must set RXDP to the address of an available

receive descriptor. While the receive state machine is active, RXDP will

follow the state machine as it advances through a linked list of available

descriptors. If the link field of the current receive descriptor is NULL

(signifying the end of the list), RXDP will not advance, but will remain on the

current descriptor. Any subsequent writes to the RXE bit of the CR register

will cause the receive state machine to reread the link field of the current

descriptor to check for new descriptors that may have been appended to

the end of the list. Software should not write to this register unless the

receive state machine is idle. Receive descriptors must be aligned on 64-bit

boundaries (A2-A0 must be zero). A 0 written to RXDP followed by a

subsequent write to RXE will cause the receiver to enter silent RX mode,

for use during WOL. In this mode packets will by received and buffered in

FIFO, but no DMA to system memory will occur. The packet data may be

recovered from the FIFO by writing a valid descriptor address to RXDP and

then strobing RXE.

2-0

unused

Tag: RXDP_HI

Size: 32 bits

Hard Reset: 00000000h

Offset: 0034h

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

31-0

RXDP_HI

Receive Descriptor Pointer

High Dword

If 64-bit addressing is enabled, this will be used as the upper 32-bits of the

current receive descriptor pointer.

DP83820 Datasheet(PDF) 51 Page - National Semiconductor (TI)

DP83820 Datasheet(HTML) 51 Page - National Semiconductor (TI)

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